--- In l..., "rolf_meeser" wrote:

>
> Hi Bob,
>
> Your first assumption is correct: Any access to CS0 address range will activate CS1 instead of CS0. Access to CS1 address range works as expected, and just activates CS1 as well. While the mirror bit is set, CS0 is never activated.
>
> As far as I can see it, it hardly makes any sense to leave the M bit set on an LPC23xx.
>
> Regards,
> Rolf
>
Rolf,

It's always nice to know what one's design will do. The clarification is greatly appreciated!

Thanks,
- Laser Plumb Bob

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--- In l..., "laserplumb" wrote:
>
> Does anyone understand exactly what the LPC-23XX Address Mirror bit 'M', in EMC Control Register (EMCControl) does??
> LPC-23XX User Manual Rev.03, Chapter 5 table 60 says that when 'M' = 1 (after reset) "chip select 1 is mirrored to the chip select 0 memory area". Does this mean that accesses to CS0 address space activate CS1, and not CS0? That seems to me to suggest that there would be no CS0 accesses in this mode, unless CS0 and CS1 activate at the same time, which could be possible. It seems ambiguous to me. Thanks for sharing! Laser Plumb Bob
>

Hi Bob,

Your first assumption is correct: Any access to CS0 address range will activate CS1 instead of CS0. Access to CS1 address range works as expected, and just activates CS1 as well. While the mirror bit is set, CS0 is never activated.

As far as I can see it, it hardly makes any sense to leave the M bit set on an LPC23xx.

Regards,
Rolf

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--- In l..., "laserplumb" wrote:
>
> Does anyone understand exactly what the LPC-23XX Address Mirror bit 'M', in EMC Control Register (EMCControl) does??
> LPC-23XX User Manual Rev.03, Chapter 5 table 60 says that when 'M' = 1 (after reset) "chip select 1 is mirrored to the chip select 0 memory area". Does this mean that accesses to CS0 address space activate CS1, and not CS0? That seems to me to suggest that there would be no CS0 accesses in this mode, unless CS0 and CS1 activate at the same time, which could be possible. It seems ambiguous to me. Thanks for sharing! Laser Plumb Bob
>
I see this worded just slightly different. Maybe a newer document ??
It says...

"Static memory chip select 1 is mirrored onto chip select 0"

without the words "memory area" which may or may not help you at all.

boB

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Does anyone understand exactly what the LPC-23XX Address Mirror bit 'M', in EMC Control Register (EMCControl) does??
LPC-23XX User Manual Rev.03, Chapter 5 table 60 says that when 'M' = 1 (after reset) "chip select 1 is mirrored to the chip select 0 memory area". Does this mean that accesses to CS0 address space activate CS1, and not CS0? That seems to me to suggest that there would be no CS0 accesses in this mode, unless CS0 and CS1 activate at the same time, which could be possible. It seems ambiguous to me. Thanks for sharing! Laser Plumb Bob

Start a New Thread