> First please forgive me for my little knowledge about embedded system.
> I am trying to design an embedded application on a Xilinx FPGA Virtex-4
> series. This has PPC405 core on it. Now i am trying to write an
> application as IP. Lets say a simple SPI cotroller. I know i have to
> interface this with PLB (Porcessor Local Bus) using IPIF module
> provided by Xilinx in EDK. What i am missing is actualy very basic idea
> here.
>
> 1. Once the 64 - bit data reaches the IP how does it been utilized by
> the IP. So when 64-bit data comes is it stored in some kind of FIFO?
>
> 2. How IP is reffered to RAM? So many times i have heard about memory
> mapping but never got a real answer. Any IP is composed of lot of
> register and all these registers have some address in memory with a
> base address as being the address of the IP and than inner register? is
> that right.
>
> 3. Can some buddy tell me the follow of data in gernel without
> application specific in FPGA.
My best advice: post your question on comp.arch.fpga.
~Dave~
Reply by Fizzy●April 26, 20062006-04-26
Hi all,
First please forgive me for my little knowledge about embedded system.
I am trying to design an embedded application on a Xilinx FPGA Virtex-4
series. This has PPC405 core on it. Now i am trying to write an
application as IP. Lets say a simple SPI cotroller. I know i have to
interface this with PLB (Porcessor Local Bus) using IPIF module
provided by Xilinx in EDK. What i am missing is actualy very basic idea
here.
1. Once the 64 - bit data reaches the IP how does it been utilized by
the IP. So when 64-bit data comes is it stored in some kind of FIFO?
2. How IP is reffered to RAM? So many times i have heard about memory
mapping but never got a real answer. Any IP is composed of lot of
register and all these registers have some address in memory with a
base address as being the address of the IP and than inner register? is
that right.
3. Can some buddy tell me the follow of data in gernel without
application specific in FPGA.
Thanks