Well to simulate these events you only have to cause them.
Give it a 0 opcode and enjoy the illegal opcode (program) exception
at $700.
Disable the FPU in the MSR, then give it an FPU opcode
and it will go to the $800 FP not available.
Make it execute and lwarx at a non-.l aligned address
and you will get a $600 alignment exception.
 The rest can be done in a more or less similar way.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
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marktxx@yahoo.com wrote:
> I have been able to successfully force a 0x0300 Data Storage exception
> (write to a bad address) and a 0x0400 Instruction Storage exception.
>
> Any ideas for generating some of the other exceptions (excluding 0x0500
> External interrupt which of course is the expected interrupt). This is
> for unit testing a module that traps these exceptions.
>
> Can a instruction simulator be used for this somehow?
> 
>   thanks
> 
>    Mark

I have been able to successfully force a 0x0300 Data Storage exception
(write to a bad address) and a 0x0400 Instruction Storage exception.

Any ideas for generating some of the other exceptions (excluding 0x0500
External interrupt which of course is the expected interrupt). This is
for unit testing a module that traps these exceptions.

Can a instruction simulator be used for this somehow?

  thanks

   Mark