There used to be thermal relief issues with a via in the middle of a pad, and I
recall wanting to use them on an RF board (to cut down inductance) but not
allowed to at the time.
Something to do with the extra heat required to heat up the solder to the
correct temperature with the extra thermal mass introduced by the via(s), but at
the same time not overcooking the components on pads without vias.
Is thermal relief still a consideration ? (assuming you have taken precautions
to solve the extra paste required for wicking).
-----Original Message-----
From: l... [mailto:l...] On Behalf Of "Pablo Nez Pcher"
Sent: Tuesday, 22 June 2010 1:34 AM
To: l...
Subject: Re: [lpc2000] Re: LPC2478 SBC and SDRAM question
In my case, assembly costs won't come into play, as I only need a couple of
boards for my project, and I will assemble them myself. However, it *is* a good
thing to know, just in case I find myself having to make more than a couple of
boards.
As for the vias in the middle of the pads, I haven't placed any on top of
them. I've spaced them a couple tens of mils, and I'm using a 208-LQFP
package, so there will be no BGA solder balls that'll wick into the via.
But then again, that's always a good thing to bear in mind.
I'm now reworking my layout with all the recommendations that you all have
given me. I'll post the new work as soon as I get it done.
Again, thank you *very* much for your help and your comments!
> Placing components on both sides of a board could
nearly double automated
> assembly cost...
>
> Placing via in the middle of the pad is fine, as long as the pad is larger
> to compensate for the extra solder needed which will wick into the via.
>
> --- In l..., "murphy8674@..." wrote:
> >
> > DS board , put memory to other side. Shorter wires, smaller board.Allso
> easier to route out peripheral because LPC has die for BGA and pins are not
> in sequence with bus.
> > Placing via in middle of pad is not very smart idea if it is not blind
> via. Otherwise when in production, all solder will wick into via and no
> contact between component and pad.
> >
>
>
--
GMX DSL: Internet-, Telefon- und Handy-Flat ab 19,99 EUR/mtl.
Bis zu 150 EUR Startguthaben inklusive! http://portal.gmx.net/de/go/dsl
In my case, assembly costs won't come into play, as I only need a couple of
boards for my project, and I will assemble them myself. However, it *is* a good
thing to know, just in case I find myself having to make more than a couple of
boards.
As for the vias in the middle of the pads, I haven't placed any on top of
them. I've spaced them a couple tens of mils, and I'm using a 208-LQFP
package, so there will be no BGA solder balls that'll wick into the via.
But then again, that's always a good thing to bear in mind.
I'm now reworking my layout with all the recommendations that you all have
given me. I'll post the new work as soon as I get it done.
Again, thank you *very* much for your help and your comments!
> Placing components on both sides of a board could
nearly double automated
> assembly cost...
>
> Placing via in the middle of the pad is fine, as long as the pad is larger
> to compensate for the extra solder needed which will wick into the via.
>
> --- In l..., "murphy8674@..." wrote:
> >
> > DS board , put memory to other side. Shorter wires, smaller board.Allso
> easier to route out peripheral because LPC has die for BGA and pins are not
> in sequence with bus.
> > Placing via in middle of pad is not very smart idea if it is not blind
> via. Otherwise when in production, all solder will wick into via and no
> contact between component and pad.
> >
--
GMX DSL: Internet-, Telefon- und Handy-Flat ab 19,99 EUR/mtl.
Bis zu 150 EUR Startguthaben inklusive! http://portal.gmx.net/de/go/dsl
Reply by bigft_id●June 21, 20102010-06-21
Placing components on both sides of a board could nearly double automated
assembly cost...
Placing via in the middle of the pad is fine, as long as the pad is larger to
compensate for the extra solder needed which will wick into the via.
--- In l..., "murphy8674@..." wrote: >
> DS board , put memory to other side. Shorter wires, smaller board.Allso easier
to route out peripheral because LPC has die for BGA and pins are not in sequence
with bus.
> Placing via in middle of pad is not very smart idea if it is not blind via.
Otherwise when in production, all solder will wick into via and no contact
between component and pad.
>
Reply by "mur...@ymail.com"●June 19, 20102010-06-19
DS board , put memory to other side. Shorter wires, smaller board.Allso easier
to route out peripheral because LPC has die for BGA and pins are not in sequence
with bus.
Placing via in middle of pad is not very smart idea if it is not blind via.
Otherwise when in production, all solder will wick into via and no contact
between component and pad.
Reply by bigft_id●June 19, 20102010-06-19
Norman already explained the timing math, I would definitely cut out all the
delay wiggles. I like to design decoupling caps with slightly larger pads, and
put a via right into the pad. That cuts down the impedance and saves board
space. I had prototype designs similar to yours running on 2 layer boards... you
have loads of leeway!
Jan
--- In l..., "Pablo Nez Pcher" wrote: >
> Hello,
>
> I'm new to this forum and this is my first post. I've been working
with microcontrollers for some time already, but only recently got into the LPC
world. My first design with an LPC microcontroller is a single board computer
based on the LPC2478, which I'm going to use for data acquisition in a
research project. Since I'm planning to run a small Linux on it, I included
SDRAM in the design, more specifically a Micron MT48LC4M32B2 128Mbit SDRAM IC.
However, being the first time I use SDRAM, I came across some questions
regarding how the tracks should be laid out. I googled info and gathered as much
as I could and, using that, I did what I could. I was wondering if anybody here
could help me. I've uploaded a picture of the top and bottom layers with
both microcontroller and SDRAM in it, here:
http://img257.imageshack.us/img257/8083/lpc2478sdram.png
>
> The specific questions are:
>
> * How probable is that my current design will work?
> * Is there any way I can improve it?
> * Will 100 nF decoupling capacitors suffice? I couldn't put some of them
on the same layer as the memory IC. Are there any chances that this may cause
problems?
> * I read that the clock line (CLKOUT) should be as long as the longest address
line. This sounds half logical, half irrational to me... could somebody please
tell me if this is how it should be?
>
> I tried to stick to the following guidelines as much as I could:
>
> * Four-layered PCB with ground and power planes (GND and PWR layers not shown
in the picture).
> * Track separation of at least 1 1/2 of track width. (I'm using 6 mil
tracks)
> * Resistors for DQMOUT, CLKOUT, CKEOUT, !RAS and !CAS lines. (I'm using
22 ohm, as in the following design:
http://www.keil.com/mcb2470/mcb2470-oem-schematics.pdf)
> * Trace length matching (Min. length: 60 milimeters, max.: 73.12). I guess
there must be some way to do better here, but it's the best I could get
with my current experience.
> * Decoupling capacitors as close to the memory IC as possible.
> * Decoupling capacitors on the same side as the memory IC.
> * Ground and power planes intact, no breaking of ground loops.
>
> More information that may be of use about the board:
>
> * Analog and digital ground planes are isolated. (The board features an
ADS1158 16-bit ADC). Ground planes communicate with the power source ground
plane through 600 ohm @ 100 MHz ferrite beads.
> * The digital power supply contains an MC34063 as a step-down regulator,
followed by a REG104-3.3 low-noise regulator.
> * The analog power supply contains two LM2673 and a REG104-5 low-noise
regulator.
> * I will be using the LCD controller.
>
> Any other information you may need, please let me know.
>
> Anything you can tell me that may help me will be very, very welcome!
> Thank you very much!
> Regards,
>
> Pablo Pölcher
> --
> GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT!
> Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01
>
Reply by Howard Hansen●June 18, 20102010-06-18
Norman,
It is a joy to come across messages like yours. Thank you for taking
the time to write a clear and through explanation.
Howard
Norman Felder wrote: >
> Hi Pablo,
>
> Your design should work just fine. It looks very conservative. I
> understand your concern regarding the design rules you've found. It
> can be hard to gauge just how important they are. Here are some
> general comments, which you should find reassuring:
>
> a) the design rules you've found are more important in larger systems
> with more chips and consequently much longer traces than yours, ie.
> designs that are pushing the limits a bit. You have a very small
> design with only one memory chip and you've located it very close to
> the processor. You're not pushing the limits. Any reasonable layout
> will probably work fine even without the effort you've gone through to
> control the signal propagation times.
>
> b) the difference in min and max trace lengths isn't even close to
> being a problem. Here's the rough calculation: on a FR4 board a
> signal propagates down a trace with a delay of about 150ps/in. In
> millimeters, that's about 5.9ps/mm. Doing the math, a signal
> travelling down your longest trace will take only about 77ps longer
> than a signal traveling down your shortest trace. In this design, you
> can safely ignore any effect that contributes less than a tenth of a
> nanosecond to your timing margins. It's just too small to be an
issue.
>
> c) The total propagation delay is approaching one nanosecond, which is
> something you should keep your eye on, but at your speed your timing
> margins should accommodate that.
>
> d) You don't have to match all the trace lengths. Let's take the
> address lines as an example. When the processor drives the address
> lines, it doesn't matter if they all arrive at the memory chip at the
> same time. What matters is that they all get there before the clock
> signal. So, it's only the longest address line that matters since
> that will be the last to arrive. If you know that the last-to-arrive
> has made it in time then you know that all the other address signals
> that traveled shorter paths also made it in time. Early is fine.
> Late is bad. There's no need to artificially increase the travel
> time of shorter address lines. In fact, removing some of the wiggles
> might tighten up the routing and thus reduce the length of the longest
> address line which will improve the margins. You can make similar
> arguments with the data lines and possibly some of the other control
> lines. (Just to be clear, this is a general argument. I don't think
> you need to change this particular layout just to possibly gain a few
> tens of picoseconds of margin.)
>
> e) The recommendation that the CLKOUT line be as long as the longest
> address line is both logical and rational if you think about what's
> going on. Everything important that happens is driven by the CLKOUT
> signal. The active edge of CLKOUT is what latches the address lines
> into the memory chip. The memory chip reacts only to what it sees at
> its' pins, after the signals have propagated to it from the
> processor. You need to be sure that all the address lines have
> arrived at the memory chip and are stable before the CLKOUT edge
> arrives. You don't want the CLKOUT signal to travel a shorter path
> and thus arrive at the memory chip earlier-than-expected relative to
> the address signals. If that were to happen the address lines might
> not have enough time to setup and become stable at the memory chip
> pins before the CLKOUT signal tells the memory chip to use them. The
> timing relationship between CLKOUT and the address lines is correct
> when the signals leave the processor pins. Make sure CLKOUT travels a
> path which is as long as the longest address line and that guarantees
> the timing relationship between CLKOUT and the address lines will
> still be correct when the signals arrive at the memory chip.
>
> f) You should be ok with a few of the decoupling capacitors on the
> opposite side of the board. That's not an uncommon practice. If
> you're worried about it, use double vias on the power and ground
> lines. That cuts the effective inductance of the vias in half which
> correspondingly improves the ability of the capacitors to do their
> job. Also, I generally use the widest traces I can to connect
> capacitors, power, and ground lines.
>
> It looks to me like you've done a great job.
>
> Best regards,
> Norman
>
>
> *From:* Pablo Núñez Pölcher
> *To:* l...
> *Sent:* Thu, June 17, 2010 4:50:22 PM
> *Subject:* [lpc2000] LPC2478 SBC and SDRAM question
>
>
>
> Hello,
>
> I'm new to this forum and this is my first post. I've been working
> with microcontrollers for some time already, but only recently got
> into the LPC world. My first design with an LPC microcontroller is a
> single board computer based on the LPC2478, which I'm going to use for
> data acquisition in a research project. Since I'm planning to run a
> small Linux on it, I included SDRAM in the design, more specifically a
> Micron MT48LC4M32B2 128Mbit SDRAM IC. However, being the first time I
> use SDRAM, I came across some questions regarding how the tracks
> should be laid out. I googled info and gathered as much as I could
> and, using that, I did what I could. I was wondering if anybody here
> could help me. I've uploaded a picture of the top and bottom layers
> with both microcontroller and SDRAM in it, here:
> http://img257.imageshack.us/img257/8083/lpc2478sdram.png
> The specific
questions are:
>
> * How probable is that my current design will work?
> * Is there any way I can improve it?
> * Will 100 nF decoupling capacitors suffice? I couldn't put some of
> them on the same layer as the memory IC. Are there any chances that
> this may cause problems?
> * I read that the clock line (CLKOUT) should be as long as the longest
> address line. This sounds half logical, half irrational to me... could
> somebody please tell me if this is how it should be?
>
> I tried to stick to the following guidelines as much as I could:
>
> * Four-layered PCB with ground and power planes (GND and PWR layers
> not shown in the picture).
> * Track separation of at least 1 1/2 of track width. (I'm using 6 mil
> tracks)
> * Resistors for DQMOUT, CLKOUT, CKEOUT, !RAS and !CAS lines. (I'm
> using 22 ohm, as in the following design:
> http://www.keil.com/mcb2470/mcb2470-oem-schematics.pdf
> )
> * Trace length matching (Min. length: 60 milimeters, max.: 73.12). I
> guess there must be some way to do better here, but it's the best I
> could get with my current experience.
> * Decoupling capacitors as close to the memory IC as possible.
> * Decoupling capacitors on the same side as the memory IC.
> * Ground and power planes intact, no breaking of ground loops.
>
> More information that may be of use about the board:
>
> * Analog and digital ground planes are isolated. (The board features
> an ADS1158 16-bit ADC). Ground planes communicate with the power
> source ground plane through 600 ohm @ 100 MHz ferrite beads.
> * The digital power supply contains an MC34063 as a step-down
> regulator, followed by a REG104-3.3 low-noise regulator.
> * The analog power supply contains two LM2673 and a REG104-5 low-noise
> regulator.
> * I will be using the LCD controller.
>
> Any other information you may need, please let me know.
>
> Anything you can tell me that may help me will be very, very welcome!
> Thank you very much!
> Regards,
>
> Pablo Pölcher
> --
> GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT!
> Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01
>
Reply by ●June 18, 20102010-06-18
Hi everybody,
thanks a lot for your help!
Herbert, it's good to know that using different trace lengths worked for
you, and the 100 MHz data is interesting!
And Norman, I *really* appreciate that you've taken the time to write such
a detailed explanation! I found it very useful and reassuring, and I will put it
all into practice right now. This will surely free up some space to route a
couple of signals which were stuck in the middle of the nightmarish wiggles.
You're right about the power and ground connections, they are missing. The
reason for this is that I haven't laid out the ground and power planes,
yet. I was planning to do so after laying out the analog and power traces.
Well, I will get back to routing now! Again, thanks a lot!
Best regards,
Pablo
-------- Original-Nachricht -------- > Datum: Fri, 18 Jun 2010 09:35:43 -0700 (PDT)
> Von: Norman Felder
> An: l...
> Betreff: Re: [lpc2000] LPC2478 SBC and SDRAM question
> Hi Pablo,
>
> Your design should work just fine. It looks very conservative. I
> understand your concern regarding the design rules you've found. It can
be hard
> to gauge just how important they are. Here are some general comments,
which
> you should find reassuring:
>
> a) the design rules you've found are more important in larger systems
with
> more chips and consequently much longer traces than yours, ie. designs
> that are pushing the limits a bit. You have a very small design with only
one
> memory chip and you've located it very close to the processor.
You're not
> pushing the limits. Any reasonable layout will probably work fine even
> without the effort you've gone through to control the signal
propagation
> times.
>
> b) the difference in min and max trace lengths isn't even close to being
a
> problem. Here's the rough calculation: on a FR4 board a signal
> propagates down a trace with a delay of about 150ps/in. In millimeters,
that's
> about 5.9ps/mm. Doing the math, a signal travelling down your longest
trace
> will take only about 77ps longer than a signal traveling down your shortest
> trace. In this design, you can safely ignore any effect that contributes
> less than a tenth of a nanosecond to your timing margins. It's just
too
> small to be an issue.
>
> c) The total propagation delay is approaching one nanosecond, which is
> something you should keep your eye on, but at your speed your timing
margins
> should accommodate that.
>
> d) You don't have to match all the trace lengths. Let's take the
address
> lines as an example. When the processor drives the address lines, it
> doesn't matter if they all arrive at the memory chip at the same time.
What
> matters is that they all get there before the clock signal. So, it's
only the
> longest address line that matters since that will be the last to arrive.
> If you know that the last-to-arrive has made it in time then you know that
> all the other address signals that traveled shorter paths also made it in
> time. Early is fine. Late is bad. There's no need to artificially
> increase the travel time of shorter address lines. In fact, removing some of
the
> wiggles might tighten up the routing and thus reduce the length of the
> longest address line which will improve the margins. You can make similar
> arguments with the data lines and possibly some of the other control lines.
> (Just to be clear, this is a general argument. I don't think you need
> to change this particular layout just to possibly gain a few tens of
> picoseconds of margin.)
>
> e) The recommendation that the CLKOUT line be as long as the longest
> address line is both logical and rational if you think about what's going
on.
> Everything important that happens is driven by the CLKOUT signal. The
> active edge of CLKOUT is what latches the address lines into the memory chip.
> The memory chip reacts only to what it sees at its' pins, after the
signals
> have propagated to it from the processor. You need to be sure that all the
> address lines have arrived at the memory chip and are stable before the
> CLKOUT edge arrives. You don't want the CLKOUT signal to travel a
shorter
> path and thus arrive at the memory chip earlier-than-expected relative to
the
> address signals. If that were to happen the address lines might not have
> enough time to setup and become stable at the memory chip pins before the
> CLKOUT signal tells the memory chip to use them. The timing relationship
> between CLKOUT and the address lines is correct when the signals leave
> the processor pins. Make sure CLKOUT travels a path which is as long as
> the longest address line and that guarantees the timing relationship
> between CLKOUT and the address lines will still be correct when the signals
> arrive at the memory chip.
>
> f) You should be ok with a few of the decoupling capacitors on the
> opposite side of the board. That's not an uncommon practice. If
you're worried
> about it, use double vias on the power and ground lines. That cuts the
> effective inductance of the vias in half which correspondingly improves the
> ability of the capacitors to do their job. Also, I generally use the
widest
> traces I can to connect capacitors, power, and ground lines.
>
> It looks to me like you've done a great job.
>
> Best regards,
> Norman
>
> ________________________________
> From: Pablo Núñez Pölcher
> To: l...
> Sent: Thu, June 17, 2010 4:50:22 PM
> Subject: [lpc2000] LPC2478 SBC and SDRAM question
>
>
> Hello,
>
> I'm new to this forum and this is my first post. I've been working
with
> microcontrollers for some time already, but only recently got into the LPC
> world. My first design with an LPC microcontroller is a single board
computer
> based on the LPC2478, which I'm going to use for data acquisition in a
> research project. Since I'm planning to run a small Linux on it, I
included
> SDRAM in the design, more specifically a Micron MT48LC4M32B2 128Mbit SDRAM
> IC. However, being the first time I use SDRAM, I came across some questions
> regarding how the tracks should be laid out. I googled info and gathered as
> much as I could and, using that, I did what I could. I was wondering if
> anybody here could help me. I've uploaded a picture of the top and
bottom
> layers with both microcontroller and SDRAM in it, here:
> http://img257.imageshack.us/img257/8083/lpc2478sdram.png
>
> The specific questions are:
>
> * How probable is that my current design will work?
> * Is there any way I can improve it?
> * Will 100 nF decoupling capacitors suffice? I couldn't put some of
them
> on the same layer as the memory IC. Are there any chances that this may
> cause problems?
> * I read that the clock line (CLKOUT) should be as long as the longest
> address line. This sounds half logical, half irrational to me... could
> somebody please tell me if this is how it should be?
>
> I tried to stick to the following guidelines as much as I could:
>
> * Four-layered PCB with ground and power planes (GND and PWR layers not
> shown in the picture).
> * Track separation of at least 1 1/2 of track width. (I'm using 6 mil
> tracks)
> * Resistors for DQMOUT, CLKOUT, CKEOUT, !RAS and !CAS lines. (I'm using
22
> ohm, as in the following design:
> http://www.keil.com/mcb2470/mcb2470-oem-schematics.pdf)
> * Trace length matching (Min. length: 60 milimeters, max.: 73.12). I guess
> there must be some way to do better here, but it's the best I could
get
> with my current experience.
> * Decoupling capacitors as close to the memory IC as possible.
> * Decoupling capacitors on the same side as the memory IC.
> * Ground and power planes intact, no breaking of ground loops.
>
> More information that may be of use about the board:
>
> * Analog and digital ground planes are isolated. (The board features an
> ADS1158 16-bit ADC). Ground planes communicate with the power source ground
> plane through 600 ohm @ 100 MHz ferrite beads.
> * The digital power supply contains an MC34063 as a step-down regulator,
> followed by a REG104-3.3 low-noise regulator.
> * The analog power supply contains two LM2673 and a REG104-5 low-noise
> regulator.
> * I will be using the LCD controller.
>
> Any other information you may need, please let me know.
>
> Anything you can tell me that may help me will be very, very welcome!
> Thank you very much!
> Regards,
>
> Pablo Pölcher
> --
> GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT!
> Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01
>
>
>
Your design should work just fine. It looks very conservative. I understand
your concern regarding the design rules you've found. It can be hard to
gauge just how important they are. Here are some general comments, which you
should find reassuring:
a) the design rules you've found are more important in larger systems with
more chips and consequently much longer traces than yours, ie. designs that are
pushing the limits a bit. You have a very small design with only one memory
chip and you've located it very close to the processor. You're not
pushing the limits. Any reasonable layout will probably work fine even without
the effort you've gone through to control the signal propagation times.
b) the difference in min and max trace lengths isn't even close to being a
problem. Here's the rough calculation: on a FR4 board a signal propagates
down a trace with a delay of about 150ps/in. In millimeters, that's about
5.9ps/mm. Doing the math, a signal travelling down your longest trace will take
only about 77ps longer than a signal traveling down your shortest trace. In
this design, you can safely ignore any effect that contributes less than a tenth
of a nanosecond to your timing margins. It's just too small to be an
issue.
c) The total propagation delay is approaching one nanosecond, which is something
you should keep your eye on, but at your speed your timing margins should
accommodate that.
d) You don't have to match all the trace lengths. Let's take the
address lines as an example. When the processor drives the address lines, it
doesn't matter if they all arrive at the memory chip at the same time.
What matters is that they all get there before the clock signal. So, it's
only the longest address line that matters since that will be the last to
arrive. If you know that the last-to-arrive has made it in time then you know
that all the other address signals that traveled shorter paths also made it in
time. Early is fine. Late is bad. There's no need to artificially
increase the travel time of shorter address lines. In fact, removing some of
the wiggles might tighten up the routing and thus reduce the length of the
longest address line which will improve the margins. You can make similar
arguments with the data lines and possibly some of the other control lines.
(Just to be clear, this is a general argument. I don't think you need
to change this particular layout just to possibly gain a few tens of
picoseconds of margin.)
e) The recommendation that the CLKOUT line be as long as the longest address
line is both logical and rational if you think about what's going on.
Everything important that happens is driven by the CLKOUT signal. The active
edge of CLKOUT is what latches the address lines into the memory chip. The
memory chip reacts only to what it sees at its' pins, after the signals
have propagated to it from the processor. You need to be sure that all the
address lines have arrived at the memory chip and are stable before the CLKOUT
edge arrives. You don't want the CLKOUT signal to travel a shorter path
and thus arrive at the memory chip earlier-than-expected relative to the address
signals. If that were to happen the address lines might not have enough time to
setup and become stable at the memory chip pins before the CLKOUT signal tells
the memory chip to use them. The timing relationship between CLKOUT and the
address lines is correct when the signals leave
the processor pins. Make sure CLKOUT travels a path which is as long as the
longest address line and that guarantees the timing relationship between CLKOUT
and the address lines will still be correct when the signals arrive at the
memory chip.
f) You should be ok with a few of the decoupling capacitors on the opposite side
of the board. That's not an uncommon practice. If you're worried
about it, use double vias on the power and ground lines. That cuts the
effective inductance of the vias in half which correspondingly improves the
ability of the capacitors to do their job. Also, I generally use the widest
traces I can to connect capacitors, power, and ground lines.
It looks to me like you've done a great job.
Best regards,
Norman
________________________________
From: Pablo Núñez Pölcher
To: l...
Sent: Thu, June 17, 2010 4:50:22 PM
Subject: [lpc2000] LPC2478 SBC and SDRAM question
Hello,
I'm new to this forum and this is my first post. I've been working
with microcontrollers for some time already, but only recently got into the LPC
world. My first design with an LPC microcontroller is a single board computer
based on the LPC2478, which I'm going to use for data acquisition in a
research project. Since I'm planning to run a small Linux on it, I included
SDRAM in the design, more specifically a Micron MT48LC4M32B2 128Mbit SDRAM IC.
However, being the first time I use SDRAM, I came across some questions
regarding how the tracks should be laid out. I googled info and gathered as much
as I could and, using that, I did what I could. I was wondering if anybody here
could help me. I've uploaded a picture of the top and bottom layers with
both microcontroller and SDRAM in it, here:
http://img257.imageshack.us/img257/8083/lpc2478sdram.png
The specific questions are:
* How probable is that my current design will work?
* Is there any way I can improve it?
* Will 100 nF decoupling capacitors suffice? I couldn't put some of them on
the same layer as the memory IC. Are there any chances that this may cause
problems?
* I read that the clock line (CLKOUT) should be as long as the longest address
line. This sounds half logical, half irrational to me... could somebody please
tell me if this is how it should be?
I tried to stick to the following guidelines as much as I could:
* Four-layered PCB with ground and power planes (GND and PWR layers not shown in
the picture).
* Track separation of at least 1 1/2 of track width. (I'm using 6 mil
tracks)
* Resistors for DQMOUT, CLKOUT, CKEOUT, !RAS and !CAS lines. (I'm using 22
ohm, as in the following design:
http://www.keil.com/mcb2470/mcb2470-oem-schematics.pdf)
* Trace length matching (Min. length: 60 milimeters, max.: 73.12). I guess there
must be some way to do better here, but it's the best I could get with my
current experience.
* Decoupling capacitors as close to the memory IC as possible.
* Decoupling capacitors on the same side as the memory IC.
* Ground and power planes intact, no breaking of ground loops.
More information that may be of use about the board:
* Analog and digital ground planes are isolated. (The board features an ADS1158
16-bit ADC). Ground planes communicate with the power source ground plane
through 600 ohm @ 100 MHz ferrite beads.
* The digital power supply contains an MC34063 as a step-down regulator,
followed by a REG104-3.3 low-noise regulator.
* The analog power supply contains two LM2673 and a REG104-5 low-noise
regulator.
* I will be using the LCD controller.
Any other information you may need, please let me know.
Anything you can tell me that may help me will be very, very welcome!
Thank you very much!
Regards,
I was just closing up your board artwork image and noticed something. It looks
like several power and ground connections are missing, such as those associated
with C29, C31, and C62, as well as those on the processor associated with C12,
C13, C14, C15, and C16. I would expect to see vias very close to those
components to make the connection to the inner power or ground planes.
Something to check. It would really suck to pay for a batch of boards with
those missing.
Cheers,
Brian
________________________________
From: Pablo Núñez Pölcher
To: l...
Sent: Thu, June 17, 2010 4:50:22 PM
Subject: [lpc2000] LPC2478 SBC and SDRAM question
Hello,
I'm new to this forum and this is my first post. I've been working
with microcontrollers for some time already, but only recently got into the LPC
world. My first design with an LPC microcontroller is a single board computer
based on the LPC2478, which I'm going to use for data acquisition in a
research project. Since I'm planning to run a small Linux on it, I included
SDRAM in the design, more specifically a Micron MT48LC4M32B2 128Mbit SDRAM IC.
However, being the first time I use SDRAM, I came across some questions
regarding how the tracks should be laid out. I googled info and gathered as much
as I could and, using that, I did what I could. I was wondering if anybody here
could help me. I've uploaded a picture of the top and bottom layers with
both microcontroller and SDRAM in it, here:
http://img257.imageshack.us/img257/8083/lpc2478sdram.png
The specific questions are:
* How probable is that my current design will work?
* Is there any way I can improve it?
* Will 100 nF decoupling capacitors suffice? I couldn't put some of them on
the same layer as the memory IC. Are there any chances that this may cause
problems?
* I read that the clock line (CLKOUT) should be as long as the longest address
line. This sounds half logical, half irrational to me... could somebody please
tell me if this is how it should be?
I tried to stick to the following guidelines as much as I could:
* Four-layered PCB with ground and power planes (GND and PWR layers not shown in
the picture).
* Track separation of at least 1 1/2 of track width. (I'm using 6 mil
tracks)
* Resistors for DQMOUT, CLKOUT, CKEOUT, !RAS and !CAS lines. (I'm using 22
ohm, as in the following design:
http://www.keil.com/mcb2470/mcb2470-oem-schematics.pdf)
* Trace length matching (Min. length: 60 milimeters, max.: 73.12). I guess there
must be some way to do better here, but it's the best I could get with my
current experience.
* Decoupling capacitors as close to the memory IC as possible.
* Decoupling capacitors on the same side as the memory IC.
* Ground and power planes intact, no breaking of ground loops.
More information that may be of use about the board:
* Analog and digital ground planes are isolated. (The board features an ADS1158
16-bit ADC). Ground planes communicate with the power source ground plane
through 600 ohm @ 100 MHz ferrite beads.
* The digital power supply contains an MC34063 as a step-down regulator,
followed by a REG104-3.3 low-noise regulator.
* The analog power supply contains two LM2673 and a REG104-5 low-noise
regulator.
* I will be using the LCD controller.
Any other information you may need, please let me know.
Anything you can tell me that may help me will be very, very welcome!
Thank you very much!
Regards,
your design is pretty fine, I would not expect *any* problems!
We've made our own board with *much* less effort (we e.g. have very
differnt lengths for the address/data traces) and it still works without
problems. I think 70 MHz is not a problem, problems would start > 100
MHz clock frequency.
Best regards
Herbert
Am 18.06.2010 00:50, schrieb "Pablo Núñez Pölcher": > Hello,
>
> I'm new to this forum and this is my first post. I've been working
with microcontrollers for some time already, but only recently got into the LPC
world. My first design with an LPC microcontroller is a single board computer
based on the LPC2478, which I'm going to use for data acquisition in a
research project. Since I'm planning to run a small Linux on it, I included
SDRAM in the design, more specifically a Micron MT48LC4M32B2 128Mbit SDRAM IC.
However, being the first time I use SDRAM, I came across some questions
regarding how the tracks should be laid out. I googled info and gathered as much
as I could and, using that, I did what I could. I was wondering if anybody here
could help me. I've uploaded a picture of the top and bottom layers with
both microcontroller and SDRAM in it, here:
http://img257.imageshack.us/img257/8083/lpc2478sdram.png
>
> The specific questions are:
>
> * How probable is that my current design will work?
> * Is there any way I can improve it?
> * Will 100 nF decoupling capacitors suffice? I couldn't put some of them
on the same layer as the memory IC. Are there any chances that this may cause
problems?
> * I read that the clock line (CLKOUT) should be as long as the longest address
line. This sounds half logical, half irrational to me... could somebody please
tell me if this is how it should be?
>
> I tried to stick to the following guidelines as much as I could:
>
> * Four-layered PCB with ground and power planes (GND and PWR layers not shown
in the picture).
> * Track separation of at least 1 1/2 of track width. (I'm using 6 mil
tracks)
> * Resistors for DQMOUT, CLKOUT, CKEOUT, !RAS and !CAS lines. (I'm using
22 ohm, as in the following design:
http://www.keil.com/mcb2470/mcb2470-oem-schematics.pdf)
> * Trace length matching (Min. length: 60 milimeters, max.: 73.12). I guess
there must be some way to do better here, but it's the best I could get
with my current experience.
> * Decoupling capacitors as close to the memory IC as possible.
> * Decoupling capacitors on the same side as the memory IC.
> * Ground and power planes intact, no breaking of ground loops.
>
> More information that may be of use about the board:
>
> * Analog and digital ground planes are isolated. (The board features an
ADS1158 16-bit ADC). Ground planes communicate with the power source ground
plane through 600 ohm @ 100 MHz ferrite beads.
> * The digital power supply contains an MC34063 as a step-down regulator,
followed by a REG104-3.3 low-noise regulator.
> * The analog power supply contains two LM2673 and a REG104-5 low-noise
regulator.
> * I will be using the LCD controller.
>
> Any other information you may need, please let me know.
>
> Anything you can tell me that may help me will be very, very welcome!
> Thank you very much!
> Regards,
>
> Pablo Pölcher
>
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Radnitzkygasse 43
A-1100 Vienna / Austria / Europe
Voice: +43-1-6894700-0
Fax: +43-1-6894700-40
Email: d...@demmel.com
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--
demmel products
Radnitzkygasse 43
A-1100 Vienna / Austria / Europe
Voice: +43-1-6894700-0
Fax: +43-1-6894700-40
Email: d...@demmel.com
WWW: http://www.demmel.com
