"Ulf Samuelsson" <ulf@a-t-m-e-l.com> wrote in message
news:e4iquo$fjm$1@emma.aioe.org...
>
> > In summary, Peter said that flash with non power-of-two block sizes has
> > extra space per block to allow for error correction and other metadata
to
> > take into account bad bits.  You, Ulf, said this was a load of dingos'
> > kidneys because the Atmel serial flash has non power-of-two block sizes
to
> > allow for error correction and other metadata to take into account bad
> > bits beyond the typical error-free lifetime of the flash.
> >
>
> Please read his post again.
> He said that any parts which has the extra bytes are inherently
unreliable.
> I.E. reading from a parallel flash with power of two are more likely to
> succeed
> without errors than reading from a part with non-power of two
> and THAT is a load of ...

Well that wasn't quite what I meant, even if thats how you take it. The
point was that the extra bytes in a sector are often intended for error
detection and correction. I that case errors might be expected in use. NAND
memories are less reliable the NOR, so NAND is more likely to need the
bytes. Of course the is just a guide, and of course you could do the
correction in power-of-two sectors, and of course you can do it with
parallel Flash, even on the fly, with a 32+7 ECC (say).

> The dataflash without use of extra bits should be as reliable as a normal
> parallel flash with 64 kB sectors.

NOR.

> > In other words, Peter is entirely correct.  It's just that the AT45 has
a
> > longer expected error-free lifetime, being NOR flash rather than NAND
> > flash.
>

I don't think that I am entirely correct,  wish I were.

Now, when is my appointment with the antipodian canine urologist...

Peter

> In summary, Peter said that flash with non power-of-two block sizes has
> extra space per block to allow for error correction and other metadata to 
> take into account bad bits.  You, Ulf, said this was a load of dingos' 
> kidneys because the Atmel serial flash has non power-of-two block sizes to 
> allow for error correction and other metadata to take into account bad 
> bits beyond the typical error-free lifetime of the flash.
>

Please read his post again.
He said that any parts which has the extra bytes are inherently unreliable.
I.E. reading from a parallel flash with power of two are more likely to 
succeed
without errors than reading from a part with non-power of two
and THAT is a load of ...

The dataflash without use of extra bits should be as reliable as a normal 
parallel flash with 64 kB sectors.

> In other words, Peter is entirely correct.  It's just that the AT45 has a 
> longer expected error-free lifetime, being NOR flash rather than NAND 
> flash.



-- 
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB

Ulf Samuelsson wrote:
>>> How about the Bad Block Management.
>>> Is it neccessary?
>> If the blocks are not power-of-two sized eg 528 then the extra bytes are
>> intended for error correction, which means errors are to be expected.
>>
>> Peter
>>
> 
> That is a load of dingos kidneys...
> Errors are to be expected in NAND flash devices, but not in NOR flash 
> devices.
> The device organisation has nothing to do with how the memory cell operates.
> 
> There is a finite number of erase cycle on any flash memory.
> Errors are ALWAYS to be expected when you are close to the limit on erase 
> cycles
> The errors that will occur, results in bits not beeing able to erase 
> properly.
> 
> The AT45 is NOR based and not NAND based so there should be no difference in 
> errors
> compared to a standard parallel flash memory.
> Adding extra bytes (like in the AT45 series) will allow you to extend the 
> life of the device BEYOND
> the 50,000-100,000 cycles specified in the device (never devices are better 
> than the original devices).
> 
> Some other key AT45 advantages are
> * Small sector size (256-1024 bytes + extra)
> * Dual SRAM databuffers allows fast read/modify write
> * Common pinout from 1 Mbit to 64 Mbit.
> 
> 
> Wear leveling is required for any flash.
> Again the extra bytes helps because you can keep wear leveling info inside
> the block.
> Simplifies a lot
> 

In summary, Peter said that flash with non power-of-two block sizes has 
extra space per block to allow for error correction and other metadata 
to take into account bad bits.  You, Ulf, said this was a load of 
dingos' kidneys because the Atmel serial flash has non power-of-two 
block sizes to allow for error correction and other metadata to take 
into account bad bits beyond the typical error-free lifetime of the flash.

In other words, Peter is entirely correct.  It's just that the AT45 has 
a longer expected error-free lifetime, being NOR flash rather than NAND 
flash.

"Ulf Samuelsson" <ulf@a-t-m-e-l.com> wrote in message
news:e4gsnt$r7s$2@gondor.sweden.atmel.com...
> >> How about the Bad Block Management.
> >> Is it neccessary?
> >
> > If the blocks are not power-of-two sized eg 528 then the extra bytes are
> > intended for error correction, which means errors are to be expected.
> >
> > Peter
> >
> That is a load of dingos kidneys...


What happened to proper attribution.
If I'm talking dingo's kidneys then at least tell everyone who said it!

> Errors are to be expected in NAND flash devices, but not in NOR flash
> devices.
> The device organisation has nothing to do with how the memory cell
operates.

No, of course not, but it is a hint at how the manufacturer expected the
device to be used. Now it code be that the device is a NOR device that
emulates a NAND part...
And... OK... do you know of any NOR parts that use non-power-of-two sectors
or NAND parts that use power-of-two but don't internally do the error
correction?

> There is a finite number of erase cycle on any flash memory.
> Errors are ALWAYS to be expected when you are close to the limit on erase
> cycles

Indeedly-doo!

> The errors that will occur, results in bits not beeing able to erase
> properly.
>
> The AT45 is NOR based and not NAND based so there should be no difference
in
> errors
> compared to a standard parallel flash memory.
> Adding extra bytes (like in the AT45 series) will allow you to extend the
> life of the device BEYOND
> the 50,000-100,000 cycles specified in the device (never devices are
better
> than the original devices).

OK, so that answers my question above.

> Some other key AT45 advantages are
> * Small sector size (256-1024 bytes + extra)
> * Dual SRAM databuffers allows fast read/modify write
> * Common pinout from 1 Mbit to 64 Mbit.
>
>
> Wear leveling is required for any flash.

Yep.

> Again the extra bytes helps because you can keep wear leveling info inside
> the block.
> Simplifies a lot

Can be very useful.

Peter

I finally found that almost all Serial Flashes uses NOR gates in their
memory cells. Error correcting mechanism is not necessary for NOR
type flashes. The wear-leveling is easy since NOR flash is byte-
programmable and leaving the factory with no bad memory cell.

Thanks for all you.
Thank you.

Jim Stewart wrote:
> York wrote:
> > I am surveying a serial flash for storing data.
> > I found the datasheet do not definitely mention the flowwing issues:
> >
> > 1. What is there, NOR or NAND type cell, in a SERIAL FLASH?
> > 2. Is a wear-leveling necessary for a serial Flash?
>
> I've been told by an authoritative source
> that SST serial flash uses exactly the same
> NOR structure as their parallel flash.

>> How about the Bad Block Management.
>> Is it neccessary?
>
> If the blocks are not power-of-two sized eg 528 then the extra bytes are
> intended for error correction, which means errors are to be expected.
>
> Peter
>

That is a load of dingos kidneys...
Errors are to be expected in NAND flash devices, but not in NOR flash 
devices.
The device organisation has nothing to do with how the memory cell operates.

There is a finite number of erase cycle on any flash memory.
Errors are ALWAYS to be expected when you are close to the limit on erase 
cycles
The errors that will occur, results in bits not beeing able to erase 
properly.

The AT45 is NOR based and not NAND based so there should be no difference in 
errors
compared to a standard parallel flash memory.
Adding extra bytes (like in the AT45 series) will allow you to extend the 
life of the device BEYOND
the 50,000-100,000 cycles specified in the device (never devices are better 
than the original devices).

Some other key AT45 advantages are
* Small sector size (256-1024 bytes + extra)
* Dual SRAM databuffers allows fast read/modify write
* Common pinout from 1 Mbit to 64 Mbit.


Wear leveling is required for any flash.
Again the extra bytes helps because you can keep wear leveling info inside
the block.
Simplifies a lot

-- 
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB

York wrote:
> I am surveying a serial flash for storing data.
> I found the datasheet do not definitely mention the flowwing issues:
> 
> 1. What is there, NOR or NAND type cell, in a SERIAL FLASH?
> 2. Is a wear-leveling necessary for a serial Flash?

I've been told by an authoritative source
that SST serial flash uses exactly the same
NOR structure as their parallel flash.

Peter Dickerson wrote:
> "York" <yukuan.jiang@gmail.com> wrote in message
> news:1147857121.450054.300740@j55g2000cwa.googlegroups.com...
> > Good Point. :)
>
> What point?
> Please quote the context so us mortals can follow.

Sorry! (I miss press the reply button.)
I means it is a good point as follows.

Peter Dickerson wrote:
> If the blocks are not power-of-two sized eg 528 then the extra bytes are
> intended for error correction, which means errors are to be expected.