Hi Ammar,
> well i have designed a system that contains
> -- altera cyclone 3 FPGA, with 50M clock
> -- altera epcs16 Flash (configuration device for cyclone3)
> -- an LPC2468 ARM processor (running uLinux),
> -- a 16M Synchronous DRAM (connected to FPGA and ARM)
> -- rest the design has ethernet, usb memory device connector, FTDI interface,
JTAG interface, ETXexpress Connector for connection to x86 system via LPC,
GPIO's, multiple power-supplies.
>
> so now i am working on a project to be developed on this design(VHDL based).
well the problem statement is to connect all 3 systems together using the
wishbone interface i.e. x86 (wishbone lpc) to FPGA (wishbone SPI) to ARM, where
x86 and ARM share the same memory space and FPGA being the center part between
these two systems.
>
> well whats done so far is the communication between x86 and FPGA via Wishbone
LPC interface and so connected to wishbone spi to ARM7, the wishbone interface
is implemented on FPGA, and in this part ARM is set to SPI master and FPGA to
SPI-slave, and only one register has been shared between x86 and ARM to prove
the communication between x86 and ARM. Now the next step is to make certain
registers of x86 accessible to ARM over wishbone, this part would be the shared
memory part between x86 and ARM. what i propose is to have a dual port RAM
implementation on FPGA which then be connected to external RAM make x86 data
accessible to ARM.
> well this is what i think, so anyone here has done this before over wishbone
interface? or may be without wishbone, i just need an idea that what i am doing
is going to right direction or not... also i am not sure about the Chip-Select
and Enable signals that will be handling the external memory access, if any idea
about that would be great.
>
> thats all for now, if i get something further i will update.
> looking forward for support from you all.
What you want in your design is:
1) x86-to-FPGA interface implemented as an
lpc-to-wishbone master interface, eg. you'd name
this component
lpc_to_wishbone_bridge.vhd
2) ARM-to-FPGA interface implemented as an
spi-to-wishbone master interface, eg. you'd name
this component
spi_to_wishbone_bridge.vhd
(Something like this might already exist).
3) The FPGA design will then have registers, RAM, etc
as wishbone slaves, i.e., you will have an
FPGA design containing two wishbone masters
communicating to a set of wishbone slaves.
The slaves will each need arbiters so that
if both master simultaneously try to access
a device, the arbiters decide who gets to go
first.
If this stuff sounds foreign to you, take a look
at the Altera Avalon bus specification, and examples,
as they show this type of design. In fact, you could
implement lpc-to-avalon and spi-to-avalon masters
and create the xx_hw.tcl scripts needed to have
the components show up in SOPB Builder, and then
construct the multi-master bus using SOPC Builder.
You should also create bus-functional-models (BFMs)
of lpc and spi read/write transactions so that you
can build a testbench with both masters and initiate
reads/writes simultaneously to a slave device. That'll
help show you have everything written correctly.
If this sounds too confusing, just contact me directly
and I can explain more (since the FPGA stuff is not LPC
specific).
Cheers,
Dave
