Reply by Roland May 25, 20062006-05-25
Mark McDougall wrote:

> For some reason it disappeared in later versions of DXP?!?
Fascinating! ;)
> Look in Library/Fpga for the constraint file for your FPGA module. In > there you'll see a section 'Burch-Style 20-Pin Headers'. > > You can simply create ports on your top-level schematic named HB[10..2] > and HA[10..2] and connect to those. There's an example in the > VideoArcadeGames - TSK51 project under Reference Designs.
Thanx a bunch! - R.
Reply by Mark McDougall May 23, 20062006-05-23
Roland wrote:

> one more Altium Designer question: how do I connect anything to a > user header on the nanoboard - the connector doesn't seem to be in > the library. Thanx!
For some reason it disappeared in later versions of DXP?!? Look in Library/Fpga for the constraint file for your FPGA module. In there you'll see a section 'Burch-Style 20-Pin Headers'. You can simply create ports on your top-level schematic named HB[10..2] and HA[10..2] and connect to those. There's an example in the VideoArcadeGames - TSK51 project under Reference Designs. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
Reply by Roland May 23, 20062006-05-23
Mark McDougall wrote:

> It's been a *long* time since I used the TSK51 on the Nanoboard but from > memory, I don't think you can actually use the external memory as > program memory?!? I don't think there's any mechanism to download a > program to the external SRAM chips.
It's possible - I succeded eventualy. The error was in the HDL memory controller, more specificaly in deselecting CS (probably some timing issues). I conected the TSK51 to external SRAM bank via my memory controler, short-circuted the internal rom in- and out-bus and took care of other related signals, pulled the pin for external memory selection high and the Designer took care of the rest. I will still have to connect the logical anylizer to the memory's pins to varify the design but the programs I tried running seem to work flawlessly. I referenced to a design from the Designer's examples folder, how to connect the TSK51 to external memory and do the SRAM/LCD/etc. memory mapping. Thanx for the effort and feel free to post any comments! Btw. does anyone know if the "after" keyword causes Xilinx VHDL synthesizer to systhesize delay circutry or is it simply ignored? And one more Altium Designer question: how do I connect anything to a user header on the nanoboard - the connector doesn't seem to be in the library. Thanx! - R.
Reply by Mark McDougall May 21, 20062006-05-21
Roland wrote:

> It could be that it's all messed-up but one thing bothers me - how do > I tell the Designer where to place my program? When using internal > FPGA memory, I can specify it as a child core and I assume that would > instruct the Designer where to place the binary. But how to do it > when using extenal chips? And what if I wanted to make the higher 64K > on the chip the program memory, could I specify that somehow?
It's been a *long* time since I used the TSK51 on the Nanoboard but from memory, I don't think you can actually use the external memory as program memory?!? I don't think there's any mechanism to download a program to the external SRAM chips. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
Reply by Roland May 21, 20062006-05-21
Hi! Sorry if this is not the right group for the question but it seems 
to be the closest to the topic I could find.

The problem is this:

I'm trying to implement a simple processor-based project on the 
NanoBoard using Altium Designer. I'm using TSK51 and external memory 
chip (128K SRAM) on the NanoBoard and my task is to connect them by 
writing a VHDL memory controller. I've created a schematic and connected 
it to the HDL and I've written a simple C-program to test the design. 
The general idea is that the external memory would function as both 
program and data memory and the controller would do the mapping - lower 
64K on the chip would act as program memory and higher 64K as data 
memory. I belive all the connections are correct and external memory is 
selected on the processor but nothing works. It could be that it's all 
messed-up but one thing bothers me - how do I tell the Designer where to 
place my program? When using internal FPGA memory, I can specify it as a 
child core and I assume that would instruct the Designer where to place 
the binary. But how to do it when using extenal chips? And what if I 
wanted to make the higher 64K on the chip the program memory, could I 
specify that somehow?

If anyone has any idea or knows where to look, I would greatly 
apprechiate it!

Thanx!

- R.