Adrian, I took a look at the web page link in your subsequent e-mail and the Low Voltage Inhibit feature is incorrect. The only devices with the LVI on-chip are the devices using the 3.3 volt regulator (see the S12VREG3V3V2/D Block User's Guide). This currently includes the 'E', 'B' and 'C' families. I will work to get the web page corrected. Regards, Gordon Adrian Vos wrote: >Is there any device feature summary for S12 which I can use to check which >versions have low voltage reset. I am only using the DP256 as it was the all >feature encompassing version when I started this project, but there may be >other versions of S12 that may have everythin I need including the low >voltage rest. Does motorla have some table with device vs features to find >other devices compatible with my requirements? > >Thanks, > >Adrian > >----- Original Message ----- >From: "Gordon Doughman" <> >To: <> >Sent: Friday, December 12, 2003 3:31 AM >Subject: Re: [68HC12] Re: EETS4K EPROT Register > >>David, >> >>Correct on both counts. Only devices NOT having the on-chip low voltage >>reset must incorporate an external LVI reset device. >> >>Regards, >>Gordon >> >>djsimpson100 wrote: >> >> >>>Gordon, >>> >>>I assume this only applies to parts without the on on chip low >>>voltage reset. I am using a E128 chip, and am relying on the onboard >>>low voltage reset. Is this OK? >>> >>>I also assume the FLASH can be corrupted as well as the EEPROM (not >>>that the the E128 as EEPROM). >>> >>>David >>> >>> >>>--- In , Gordon Doughman <g.doughman@m...> wrote: >>> >>> >>>>Adrian, >>>> >>>>Your design MUST incorporate a a power up/down reset device. This >>>> >>>> >>>device must pull reset low when Vdd falls below the specified minimum >>>operating voltage and must keep reset low until Vdd falls below 1 >>>volt. Using the protection mechanism of the EEPROM will not prevent >>>corruption of the EEPROM during power up/down since the logic >>>associated with the protection mechanism (or any of the other >>>circuitry) is not characterized to operate when Vdd is outside the >>>specified operating levels. >>> >>> >>>>Bottom line is that you will need to incorporate a power up/down >>>> >>>> >>>reset device into your hardware design. >>> >>> >>>>Regards, >>>>Gordon >>>> >>>>Adrian Vos wrote: >>>> >>>> >>>> >>>>>Hi All, >>>>> >>>>>I am playing with the EETS4K module on a DP256. I am using this >>>>> >>>>> >>>memory space >>> >>> >>>>>to hold configurable data that can be altered by serial connected >>>>> >>>>> >>>PC >>> >>> >>>>>software. I find that this memory occasionally gets erased on >>>>> >>>>> >>>power up or >>> >>> >>>>>shutdown, and I think it could be due to not using a reset chip. I >>>>> >>>>> >>>was >>> >>> >>>>>thinking about working around this problem by setting the >>>>> >>>>> >>>protection >>> >>> >>>>>register for this memory to protect the EEPROM when I am not >>>>> >>>>> >>>programming it, >>> >>> >>>>>but I cannot see that this can be done. From the documentation, the >>>>>protection can be enabled when in the disabled state, but there is >>>>> >>>>> >>>no way to >>> >>> >>>>>diable the protection from the enabled state in my code. The >>>>> >>>>> >>>actual state of >>> >>> >>>>>the regeister is located from one byte of the EEPROM on a reset, >>>>> >>>>> >>>and I >>> >>> >>>>>currently set this to unprotected. I can then protect by whriting >>>>> >>>>> >>>to the >>> >>> >>>>>EPROT register, but once protected, the only way to unprotect it >>>>> >>>>> >>>is to >>> >>> >>>>>reset. Am I understanding this correctly? Is there any workaround? >>>>> >>>>> >>>I can >>> >>> >>>>>understand the need to make it difficult to unprotect the EEPROM, >>>>> >>>>> >>>but is >>> >>> >>>>>there any way to use this feature to prevent erasure of the EETS4K >>>>> >>>>> >>>due to no >>> >>> >>>>>use of a reset chip? >>>>> >>>>>Cheers, >>>>> >>>>>Adrian >>>>> >>>>> >>>>> >>>>>-------------------- >>>>> >>>>> >>>>> >>>>>">http://docs.yahoo.com/info/terms/ >>> >>> >>>>> >>>>> >>>>-- >>>>=============================================================== >>>>Gordon Doughman Ph: 937-438-6811 >>>>Motorola Semiconductor Fax: 937-434-7457 >>>>Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 >>>>Suite 175 >>>>3131 Newmark Drive >>>>Miamisburg, OH 45342 >>>> >>>>Check out my HC12 book at: >>>>http://www.rtcbooks.com/programming.php >>>> >>>> >>> >>> >>>-------------------- >>> >>> >>> >>>">http://docs.yahoo.com/info/terms/ >>> >>> >>> >>> >>-- >>=============================================================== >>Gordon Doughman Ph: 937-438-6811 >>Motorola Semiconductor Fax: 937-434-7457 >>Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 >>Suite 175 >>3131 Newmark Drive >>Miamisburg, OH 45342 >> >>Check out my HC12 book at: >>http://www.rtcbooks.com/programming.php >> >> >> >> >> >>-------------------- >> >> >> >>">http://docs.yahoo.com/info/terms/ >> > > >-------------------- > >">http://docs.yahoo.com/info/terms/ > -- =============================================================== Gordon Doughman Ph: 937-438-6811 Motorola Semiconductor Fax: 937-434-7457 Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 Suite 175 3131 Newmark Drive Miamisburg, OH 45342 Check out my HC12 book at: http://www.rtcbooks.com/programming.php

Hi All, Further to my last message, I have done some searching for devices which suit my requirements, but have the low voltage reset feature that some S12 deviced have so a external reset chip is not required. On the motorola site, in the product description of motorla Automotive S12 devices: http://e-www.motorola.com/webapp/sps/site/taxonomy.jsp?nodeIdt3ZGpnLn8636bJwn The S12DP256B (which I am using) has listed in other peripherals: Low Voltage Inhibit, which seems to be the feature I am after, but I cannot see any evidence in the 256B documents to support this fact. Is 'Low Voltage Inhibit' what I think it is? Does the DP256B actually have it, or is this an error on the motorola site? Possibly later masks have it and earlier not, but there is no evideince of this in the erata? At the end of the day, I am just trying to find out if I buy 1000 latest mask DP256B devices to make some products, can I do without a reset chip (and use my current PCB design), or do I need to redesign a PCB with the reset chip external? It seems that the DP variety of devices suits my requirements best as I need: * 8 Timer channels * 8PWM channels * 8 ATD channels * 4kEEPROM It seems that only devices without these features include a LVI, but awaiting a response to my question above to confirm this. Cheers, Adrian ----- Original Message ----- From: "Gordon Doughman" <> To: <> Sent: Friday, December 12, 2003 3:31 AM Subject: Re: [68HC12] Re: EETS4K EPROT Register > David, > > Correct on both counts. Only devices NOT having the on-chip low voltage > reset must incorporate an external LVI reset device. > > Regards, > Gordon > > djsimpson100 wrote: > > >Gordon, > > > >I assume this only applies to parts without the on on chip low > >voltage reset. I am using a E128 chip, and am relying on the onboard > >low voltage reset. Is this OK? > > > >I also assume the FLASH can be corrupted as well as the EEPROM (not > >that the the E128 as EEPROM). > > > >David > > > > > >--- In , Gordon Doughman <g.doughman@m...> wrote: > > > >>Adrian, > >> > >>Your design MUST incorporate a a power up/down reset device. This > >> > >device must pull reset low when Vdd falls below the specified minimum > >operating voltage and must keep reset low until Vdd falls below 1 > >volt. Using the protection mechanism of the EEPROM will not prevent > >corruption of the EEPROM during power up/down since the logic > >associated with the protection mechanism (or any of the other > >circuitry) is not characterized to operate when Vdd is outside the > >specified operating levels. > > > >>Bottom line is that you will need to incorporate a power up/down > >> > >reset device into your hardware design. > > > >>Regards, > >>Gordon > >> > >>Adrian Vos wrote: > >> > >> > >>>Hi All, > >>> > >>>I am playing with the EETS4K module on a DP256. I am using this > >>> > >memory space > > > >>>to hold configurable data that can be altered by serial connected > >>> > >PC > > > >>>software. I find that this memory occasionally gets erased on > >>> > >power up or > > > >>>shutdown, and I think it could be due to not using a reset chip. I > >>> > >was > > > >>>thinking about working around this problem by setting the > >>> > >protection > > > >>>register for this memory to protect the EEPROM when I am not > >>> > >programming it, > > > >>>but I cannot see that this can be done. From the documentation, the > >>>protection can be enabled when in the disabled state, but there is > >>> > >no way to > > > >>>diable the protection from the enabled state in my code. The > >>> > >actual state of > > > >>>the regeister is located from one byte of the EEPROM on a reset, > >>> > >and I > > > >>>currently set this to unprotected. I can then protect by whriting > >>> > >to the > > > >>>EPROT register, but once protected, the only way to unprotect it > >>> > >is to > > > >>>reset. Am I understanding this correctly? Is there any workaround? > >>> > >I can > > > >>>understand the need to make it difficult to unprotect the EEPROM, > >>> > >but is > > > >>>there any way to use this feature to prevent erasure of the EETS4K > >>> > >due to no > > > >>>use of a reset chip? > >>> > >>>Cheers, > >>> > >>>Adrian > >>> > >>> > >>> > >>>-------------------- > >>> > >>> > >>> > >>>">http://docs.yahoo.com/info/terms/ > > > >>> > >>> > >>> > >>-- > >>=============================================================== > >>Gordon Doughman Ph: 937-438-6811 > >>Motorola Semiconductor Fax: 937-434-7457 > >>Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > >>Suite 175 > >>3131 Newmark Drive > >>Miamisburg, OH 45342 > >> > >>Check out my HC12 book at: > >>http://www.rtcbooks.com/programming.php > >> > > > > > > > >-------------------- > > > > > > > >">http://docs.yahoo.com/info/terms/ > > > > > > > > -- > =============================================================== > Gordon Doughman Ph: 937-438-6811 > Motorola Semiconductor Fax: 937-434-7457 > Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > Suite 175 > 3131 Newmark Drive > Miamisburg, OH 45342 > > Check out my HC12 book at: > http://www.rtcbooks.com/programming.php > -------------------- > > ">http://docs.yahoo.com/info/terms/ >

Is there any device feature summary for S12 which I can use to check which versions have low voltage reset. I am only using the DP256 as it was the all feature encompassing version when I started this project, but there may be other versions of S12 that may have everythin I need including the low voltage rest. Does motorla have some table with device vs features to find other devices compatible with my requirements? Thanks, Adrian ----- Original Message ----- From: "Gordon Doughman" <> To: <> Sent: Friday, December 12, 2003 3:31 AM Subject: Re: [68HC12] Re: EETS4K EPROT Register > David, > > Correct on both counts. Only devices NOT having the on-chip low voltage > reset must incorporate an external LVI reset device. > > Regards, > Gordon > > djsimpson100 wrote: > > >Gordon, > > > >I assume this only applies to parts without the on on chip low > >voltage reset. I am using a E128 chip, and am relying on the onboard > >low voltage reset. Is this OK? > > > >I also assume the FLASH can be corrupted as well as the EEPROM (not > >that the the E128 as EEPROM). > > > >David > > > > > >--- In , Gordon Doughman <g.doughman@m...> wrote: > > > >>Adrian, > >> > >>Your design MUST incorporate a a power up/down reset device. This > >> > >device must pull reset low when Vdd falls below the specified minimum > >operating voltage and must keep reset low until Vdd falls below 1 > >volt. Using the protection mechanism of the EEPROM will not prevent > >corruption of the EEPROM during power up/down since the logic > >associated with the protection mechanism (or any of the other > >circuitry) is not characterized to operate when Vdd is outside the > >specified operating levels. > > > >>Bottom line is that you will need to incorporate a power up/down > >> > >reset device into your hardware design. > > > >>Regards, > >>Gordon > >> > >>Adrian Vos wrote: > >> > >> > >>>Hi All, > >>> > >>>I am playing with the EETS4K module on a DP256. I am using this > >>> > >memory space > > > >>>to hold configurable data that can be altered by serial connected > >>> > >PC > > > >>>software. I find that this memory occasionally gets erased on > >>> > >power up or > > > >>>shutdown, and I think it could be due to not using a reset chip. I > >>> > >was > > > >>>thinking about working around this problem by setting the > >>> > >protection > > > >>>register for this memory to protect the EEPROM when I am not > >>> > >programming it, > > > >>>but I cannot see that this can be done. From the documentation, the > >>>protection can be enabled when in the disabled state, but there is > >>> > >no way to > > > >>>diable the protection from the enabled state in my code. The > >>> > >actual state of > > > >>>the regeister is located from one byte of the EEPROM on a reset, > >>> > >and I > > > >>>currently set this to unprotected. I can then protect by whriting > >>> > >to the > > > >>>EPROT register, but once protected, the only way to unprotect it > >>> > >is to > > > >>>reset. Am I understanding this correctly? Is there any workaround? > >>> > >I can > > > >>>understand the need to make it difficult to unprotect the EEPROM, > >>> > >but is > > > >>>there any way to use this feature to prevent erasure of the EETS4K > >>> > >due to no > > > >>>use of a reset chip? > >>> > >>>Cheers, > >>> > >>>Adrian > >>> > >>> > >>> > >>>-------------------- > >>> > >>> > >>> > >>>">http://docs.yahoo.com/info/terms/ > > > >>> > >>> > >>> > >>-- > >>=============================================================== > >>Gordon Doughman Ph: 937-438-6811 > >>Motorola Semiconductor Fax: 937-434-7457 > >>Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > >>Suite 175 > >>3131 Newmark Drive > >>Miamisburg, OH 45342 > >> > >>Check out my HC12 book at: > >>http://www.rtcbooks.com/programming.php > >> > > > > > > > >-------------------- > > > > > > > >">http://docs.yahoo.com/info/terms/ > > > > > > > > -- > =============================================================== > Gordon Doughman Ph: 937-438-6811 > Motorola Semiconductor Fax: 937-434-7457 > Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > Suite 175 > 3131 Newmark Drive > Miamisburg, OH 45342 > > Check out my HC12 book at: > http://www.rtcbooks.com/programming.php > -------------------- > > ">http://docs.yahoo.com/info/terms/ >

David, Correct on both counts. Only devices NOT having the on-chip low voltage reset must incorporate an external LVI reset device. Regards, Gordon djsimpson100 wrote: >Gordon, > >I assume this only applies to parts without the on on chip low >voltage reset. I am using a E128 chip, and am relying on the onboard >low voltage reset. Is this OK? > >I also assume the FLASH can be corrupted as well as the EEPROM (not >that the the E128 as EEPROM). > >David >--- In , Gordon Doughman <g.doughman@m...> wrote: > >>Adrian, >> >>Your design MUST incorporate a a power up/down reset device. This >> >device must pull reset low when Vdd falls below the specified minimum >operating voltage and must keep reset low until Vdd falls below 1 >volt. Using the protection mechanism of the EEPROM will not prevent >corruption of the EEPROM during power up/down since the logic >associated with the protection mechanism (or any of the other >circuitry) is not characterized to operate when Vdd is outside the >specified operating levels. > >>Bottom line is that you will need to incorporate a power up/down >> >reset device into your hardware design. > >>Regards, >>Gordon >> >>Adrian Vos wrote: >> >> >>>Hi All, >>> >>>I am playing with the EETS4K module on a DP256. I am using this >>> >memory space > >>>to hold configurable data that can be altered by serial connected >>> >PC > >>>software. I find that this memory occasionally gets erased on >>> >power up or > >>>shutdown, and I think it could be due to not using a reset chip. I >>> >was > >>>thinking about working around this problem by setting the >>> >protection > >>>register for this memory to protect the EEPROM when I am not >>> >programming it, > >>>but I cannot see that this can be done. From the documentation, the >>>protection can be enabled when in the disabled state, but there is >>> >no way to > >>>diable the protection from the enabled state in my code. The >>> >actual state of > >>>the regeister is located from one byte of the EEPROM on a reset, >>> >and I > >>>currently set this to unprotected. I can then protect by whriting >>> >to the > >>>EPROT register, but once protected, the only way to unprotect it >>> >is to > >>>reset. Am I understanding this correctly? Is there any workaround? >>> >I can > >>>understand the need to make it difficult to unprotect the EEPROM, >>> >but is > >>>there any way to use this feature to prevent erasure of the EETS4K >>> >due to no > >>>use of a reset chip? >>> >>>Cheers, >>> >>>Adrian >>> >>> >>> >>>-------------------- >>> >>> >>> >>>">http://docs.yahoo.com/info/terms/ > >>> >>> >>> >>-- >>=============================================================== >>Gordon Doughman Ph: 937-438-6811 >>Motorola Semiconductor Fax: 937-434-7457 >>Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 >>Suite 175 >>3131 Newmark Drive >>Miamisburg, OH 45342 >> >>Check out my HC12 book at: >>http://www.rtcbooks.com/programming.php > > >-------------------- > >">http://docs.yahoo.com/info/terms/ > -- =============================================================== Gordon Doughman Ph: 937-438-6811 Motorola Semiconductor Fax: 937-434-7457 Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 Suite 175 3131 Newmark Drive Miamisburg, OH 45342 Check out my HC12 book at: http://www.rtcbooks.com/programming.php

Gordon, I assume this only applies to parts without the on on chip low voltage reset. I am using a E128 chip, and am relying on the onboard low voltage reset. Is this OK? I also assume the FLASH can be corrupted as well as the EEPROM (not that the the E128 as EEPROM). David --- In , Gordon Doughman <g.doughman@m...> wrote: > Adrian, > > Your design MUST incorporate a a power up/down reset device. This device must pull reset low when Vdd falls below the specified minimum operating voltage and must keep reset low until Vdd falls below 1 volt. Using the protection mechanism of the EEPROM will not prevent corruption of the EEPROM during power up/down since the logic associated with the protection mechanism (or any of the other circuitry) is not characterized to operate when Vdd is outside the specified operating levels. > > Bottom line is that you will need to incorporate a power up/down reset device into your hardware design. > > Regards, > Gordon > > Adrian Vos wrote: > > >Hi All, > > > >I am playing with the EETS4K module on a DP256. I am using this memory space > >to hold configurable data that can be altered by serial connected PC > >software. I find that this memory occasionally gets erased on power up or > >shutdown, and I think it could be due to not using a reset chip. I was > >thinking about working around this problem by setting the protection > >register for this memory to protect the EEPROM when I am not programming it, > >but I cannot see that this can be done. From the documentation, the > >protection can be enabled when in the disabled state, but there is no way to > >diable the protection from the enabled state in my code. The actual state of > >the regeister is located from one byte of the EEPROM on a reset, and I > >currently set this to unprotected. I can then protect by whriting to the > >EPROT register, but once protected, the only way to unprotect it is to > >reset. Am I understanding this correctly? Is there any workaround? I can > >understand the need to make it difficult to unprotect the EEPROM, but is > >there any way to use this feature to prevent erasure of the EETS4K due to no > >use of a reset chip? > > > >Cheers, > > > >Adrian > > > > > > > >-------------------- > > > > > > > >">http://docs.yahoo.com/info/terms/ > > > > > > > > > > -- > =============================================================== > Gordon Doughman Ph: 937-438-6811 > Motorola Semiconductor Fax: 937-434-7457 > Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > Suite 175 > 3131 Newmark Drive > Miamisburg, OH 45342 > > Check out my HC12 book at: > http://www.rtcbooks.com/programming.php

Check www.maxim-ic.com <www.maxim-ic.com> for the supervisory ccts. The one we use with the dg128a is the MAX6402BS31, I don't have the BOM here, but I think we were using the bump package. I would not recommend that unless you are really tight on board space. We are going to switch to another package, its really intended for cell phones so I am told. Somethings to watch for are, * the reset level you want to trigger at, * push pull configuration, * whether you want a switch input to the cct, * or just a voltage level triggered reset, * and the package configuration. The pricing is on the web site, and you can order samples without charge. The support has been good for us. Bob Lewis

Hello Adrian, The EVB i' currently working with uses a Maxim-Dallas MAX6421 which is a very compact surface mount device and only requires one external capacitor. Good luck! Robert > >I was hoping to find a work around using my existing PCB design, but it >looks like this is not possible. If you read the crg manual, you get the >impression delay after reset feature is enough to not require a reset chip, >but it looks like a reset chip is definately required. I know this has been >done before, but can anyone recommend a suitable reset chip that is easy to >get, compact (surface mount), and cheap. I will incorporate this on a new >revision which must now be done to the PCB. > >Cheers, > >Adrian

MAX6326 series. SOT23, standalone. push-pill and open-drain output versions. Analog Device has equivalents. Nick > -----Original Message----- > From: Adrian Vos [mailto:] > Sent: Monday, December 08, 2003 5:09 PM > To: > Subject: Re: [68HC12] EETS4K EPROT Register > Thanks Gordon, > > I was hoping to find a work around using my existing PCB > design, but it > looks like this is not possible. If you read the crg manual, > you get the > impression delay after reset feature is enough to not require > a reset chip, > but it looks like a reset chip is definately required. I know > this has been > done before, but can anyone recommend a suitable reset chip > that is easy to > get, compact (surface mount), and cheap. I will incorporate > this on a new > revision which must now be done to the PCB. > > Cheers, > > Adrian > > ----- Original Message ----- > From: "Gordon Doughman" <> > To: <> > Sent: Tuesday, December 09, 2003 2:04 AM > Subject: Re: [68HC12] EETS4K EPROT Register > > Adrian, > > > > Your design MUST incorporate a a power up/down reset > device. This device > must pull reset low when Vdd falls below the specified > minimum operating > voltage and must keep reset low until Vdd falls below 1 volt. > Using the > protection mechanism of the EEPROM will not prevent > corruption of the EEPROM > during power up/down since the logic associated with the protection > mechanism (or any of the other circuitry) is not > characterized to operate > when Vdd is outside the specified operating levels. > > > > Bottom line is that you will need to incorporate a power > up/down reset > device into your hardware design. > > > > Regards, > > Gordon > > > > Adrian Vos wrote: > > > > >Hi All, > > > > > >I am playing with the EETS4K module on a DP256. I am using > this memory > space > > >to hold configurable data that can be altered by serial > connected PC > > >software. I find that this memory occasionally gets erased > on power up or > > >shutdown, and I think it could be due to not using a reset > chip. I was > > >thinking about working around this problem by setting the > protection > > >register for this memory to protect the EEPROM when I am > not programming > it, > > >but I cannot see that this can be done. From the documentation, the > > >protection can be enabled when in the disabled state, but > there is no way > to > > >diable the protection from the enabled state in my code. > The actual state > of > > >the regeister is located from one byte of the EEPROM on a > reset, and I > > >currently set this to unprotected. I can then protect by > whriting to the > > >EPROT register, but once protected, the only way to > unprotect it is to > > >reset. Am I understanding this correctly? Is there any > workaround? I can > > >understand the need to make it difficult to unprotect the > EEPROM, but is > > >there any way to use this feature to prevent erasure of > the EETS4K due to > no > > >use of a reset chip? > > > > > >Cheers, > > > > > >Adrian > > > > > > > > > > > >-------------------- > > > > > > > > > > > >">http://docs.yahoo.com/info/terms/ > > > > > > > > > > > > > > > > -- > > =============================================================== > > Gordon Doughman Ph: 937-438-6811 > > Motorola Semiconductor Fax: 937-434-7457 > > Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > > Suite 175 > > 3131 Newmark Drive > > Miamisburg, OH 45342 > > > > Check out my HC12 book at: > > http://www.rtcbooks.com/programming.php > > > > > > > > > > > > -------------------- > > > > > > > > ">http://docs.yahoo.com/info/terms/ > > ------------------------ Yahoo! Groups Sponsor > ---------------------~--> > Buy Ink Cartridges or Refill Kits for your HP, Epson, Canon or Lexmark > Printer at MyInks.com. Free s/h on orders $50 or more to the > US & Canada. > http://www.c1tracking.com/l.asp?cidU11 > http://us.click.yahoo.com/mOAaAA/3exGAA/qnsNAA/dN_tlB/TM > -------------------------- > -------~-> > > -------------------- > > ">http://docs.yahoo.com/info/terms/

Adrian Vos wrote: > looks like this is not possible. If you read the crg manual, you get the > impression delay after reset feature is enough to not require a reset chip, > but it looks like a reset chip is definately required. I know this has been right, it's not so easy to find. In the HC12 docs it's a good idea to look for all occurances of "runaway". In the S12 docs, I still found no equivalent. It would be nice to have those pitfalls mentioned more conspicuous in the docs. > done before, but can anyone recommend a suitable reset chip that is easy to > get, compact (surface mount), and cheap. I will incorporate this on a new there was a long thread 2-1/2 weeks ago (2003-11-20...2003-11-23) about the (likely) cheapest available reset chips *809 and *803, how to use them (using 809 with totem pole output) and where to buy (ON, NS, Fairchild...). Oliver -- Oliver Betz, Muenchen

Thanks Gordon, I was hoping to find a work around using my existing PCB design, but it looks like this is not possible. If you read the crg manual, you get the impression delay after reset feature is enough to not require a reset chip, but it looks like a reset chip is definately required. I know this has been done before, but can anyone recommend a suitable reset chip that is easy to get, compact (surface mount), and cheap. I will incorporate this on a new revision which must now be done to the PCB. Cheers, Adrian ----- Original Message ----- From: "Gordon Doughman" <> To: <> Sent: Tuesday, December 09, 2003 2:04 AM Subject: Re: [68HC12] EETS4K EPROT Register > Adrian, > > Your design MUST incorporate a a power up/down reset device. This device must pull reset low when Vdd falls below the specified minimum operating voltage and must keep reset low until Vdd falls below 1 volt. Using the protection mechanism of the EEPROM will not prevent corruption of the EEPROM during power up/down since the logic associated with the protection mechanism (or any of the other circuitry) is not characterized to operate when Vdd is outside the specified operating levels. > > Bottom line is that you will need to incorporate a power up/down reset device into your hardware design. > > Regards, > Gordon > > Adrian Vos wrote: > > >Hi All, > > > >I am playing with the EETS4K module on a DP256. I am using this memory space > >to hold configurable data that can be altered by serial connected PC > >software. I find that this memory occasionally gets erased on power up or > >shutdown, and I think it could be due to not using a reset chip. I was > >thinking about working around this problem by setting the protection > >register for this memory to protect the EEPROM when I am not programming it, > >but I cannot see that this can be done. From the documentation, the > >protection can be enabled when in the disabled state, but there is no way to > >diable the protection from the enabled state in my code. The actual state of > >the regeister is located from one byte of the EEPROM on a reset, and I > >currently set this to unprotected. I can then protect by whriting to the > >EPROT register, but once protected, the only way to unprotect it is to > >reset. Am I understanding this correctly? Is there any workaround? I can > >understand the need to make it difficult to unprotect the EEPROM, but is > >there any way to use this feature to prevent erasure of the EETS4K due to no > >use of a reset chip? > > > >Cheers, > > > >Adrian > > > > > > > >-------------------- > > > > > > > >">http://docs.yahoo.com/info/terms/ > > > > > > > > > > -- > =============================================================== > Gordon Doughman Ph: 937-438-6811 > Motorola Semiconductor Fax: 937-434-7457 > Field Applications Engineer Pager: 800-759-8352 Pin: 1304089 > Suite 175 > 3131 Newmark Drive > Miamisburg, OH 45342 > > Check out my HC12 book at: > http://www.rtcbooks.com/programming.php > -------------------- > > ">http://docs.yahoo.com/info/terms/ >