> PC> No, I don't think so. ARM don't
publish who licenses what in
> PC> detail. When you read datasheets you can generally figure out the
> PC> similarities between peripherals.
>
> You can also scan the register blocks for the PrimeCell IDs. All
> standard PLxxx peripherals seem to have the PrimeCell ID (0xB105F00D)
> at 0x0FF0 and peripheral ID at 0x0FE0. Here's a quick and dirty
scanner
> that seems to work on my LPC1768:
Indeed, but you can get this by just reading the manual. :-) You'll
find
the CoreSight components can also be scanned, and not just on Cortex-M.
Some devices, such as the iMX51, are broken in this respect as the DAP
doesn't have the correct entry for the ROM table...
Reply by Igor Skochinsky●January 21, 20112011-01-21
Hello Paul,
Friday, January 21, 2011, 10:20:06 AM, you wrote:
PC> No, I don't think so. ARM don't publish who licenses what in
detail. When
PC> you read datasheets you can generally figure out the similarities between
PC> peripherals.
You can also scan the register blocks for the PrimeCell IDs. All
standard PLxxx peripherals seem to have the PrimeCell ID (0xB105F00D)
at 0x0FF0 and peripheral ID at 0x0FE0. Here's a quick and dirty scanner
that
seems to work on my LPC1768:
extern "C" void HardFault_Handler() { printf("Hard Fault!\n"); while(1); }
> > No, I don't think so.
> > ARM don't publish who licenses what in detail.
> > When you read datasheets you can generally figure out the
> similarities
> > between peripherals.
>
> i have not followed this thread in detail nor spend a lot time on
> reading last email, but there are some identification register (in each
> peripheral ?) at least i think i have seen them on Cortex-M3, but never
> used / accessed them.
> Is there a way to recognize it through them ?
> So you just need a small programm to read and decode this info...
That's true for PrimeCell peripherals; and it's true for CoreSight
components. You can identify CoreSight components through the DAP using the
ROM table. Other peripherals may well not have IDs associated with them.
However, a look at the user manual for the chip usually tells you all you
need to know.
-- Paul.
Reply by capiman26061973●January 21, 20112011-01-21
Hello,
> No, I don't think so.
> ARM don't publish who licenses what in detail.
> When you read datasheets you can generally figure out the
> similarities between peripherals.
i have not followed this thread in detail nor spend a lot time
on reading last email, but there are some identification register
(in each peripheral ?) at least i think i have seen them on Cortex-M3,
but never used / accessed them.
Is there a way to recognize it through them ?
So you just need a small programm to read and decode
this info...
Best regards,
Martin
Reply by Paul Curtis●January 21, 20112011-01-21
Hi,
> > The SSP port is licensed from ARM, it's a
PrimeCell PL022, and is on
> many, many devices--not just LPCs (STR910 has one, as done LM3S
> silicon).
>
> I've been googling, but can't find this.
PL022: (SSP, LM3S manuals call it an SSI)
PL080: (LPC1700 + others, DMA controller)
PL230: (uDMAC, on quite a few M3s now)
> Besides just comparing
> datasheets of MCUs, is there a way to find out where PL022 (and other
> primecell peripherals) are used?
No, I don't think so. ARM don't publish who licenses what in detail.
When
you read datasheets you can generally figure out the similarities between
peripherals.
> The SSP port is licensed from ARM, it's a
PrimeCell PL022, and is on many, many devices--not just LPCs (STR910 has one, as
done LM3S silicon).
I've been googling, but can't find this. Besides just comparing
datasheets of MCUs, is there a way to find out where PL022 (and other primecell
peripherals) are used?
Reply by Scott●January 19, 20112011-01-19
Hi Olivier
MBED only brings out a sub-set of the pins of the LPC1768. I'll upload a
spreadsheet I created showing this.
-Scott
--- In l..., Olivier Gautherot wrote:
>
> Unfortunately, I am still working on the schematics and hope to produce the
> board during February so I won't have hardware for the next weeks.
Does
> anyone have a board to find out? I checked the Mbed board and it has only 2
> SPI ports so back to square 1 - this seems to support Paul's
statement.
>
> Cheers
> --
> Olivier Gautherot
> olivier@...
>
Reply by David Smead●January 19, 20112011-01-19
You can use SPI or SSP0, but not both.
On Wed, Jan 19, 2011 at 6:39 PM, Olivier Gautherot wrote:
> Hi Scott,
> On Wed, Jan 19, 2011 at 11:03 PM, Scott wrote:
>
>> No, there are separate sets of pins for SPI/SSP0/SSP1 even on the
>> LQFP80 package. There are also three interrupt vectors and three sets of
>> registers, so the statement in the user manual doesn't appear to make
sense.
>> Can you try it out?
>> -Scott
>> Unfortunately, I am still working on the schematics and hope to produce
the
> board during February so I won't have hardware for the next weeks.
Does
> anyone have a board to find out? I checked the Mbed board and it has only 2
> SPI ports so back to square 1 - this seems to support Paul's
statement.
>
> Cheers
> --
> Olivier Gautherot
> o...@gautherot.net
>
>
>
Reply by Olivier Gautherot●January 19, 20112011-01-19
Hi Daniel,
On Wed, Jan 19, 2011 at 11:53 PM, Daniel Widyanto
> wrote:
> Hi Oliver,
>
> Basically, the remark in LPC17xx User Manual was meant to make the user
> using SSP0, instead of SPI. But it doesn't mean that SSP0 and SPI cannot
run
> at the same time.
>
Great news. I understand that SSP has better performance that SPI - but SPI
has the advantage of existing beside the SSP channels (that will be busy on
other things...) SPI will be enough for the uC communication.
I'll plan the eval board with a set of 0-ohm resistors to ensure that
the
SSP/SPI buses can be rerouted if necessary and also make sure that the 3
buses can be supported (assuming they work).
Cheers
--
Olivier Gautherot
o...@gautherot.net
Reply by Daniel Widyanto●January 19, 20112011-01-19
Hi Oliver,
Basically, the remark in LPC17xx User Manual was meant to make the user using
SSP0, instead of SPI.But it doesn't mean that SSP0 and SPI cannot run at
the same time.
For detailed info, LPC17xx has three SPI-compatible peripherals that can be run
altogether:*) SPI peripheral:-> Pins: P0.15/SCK, P0.16/SSEL, P0.17/MISO,
P0.18/MOSI-> Max SCK for master mode: 100Mhz / 8 = 12.5Mhz-> Max SCK for slave
mode: 100Mhz / 8 = 12.5Mhz*) SSP0 peripheral:-> Pins: P1.20/SCK0, P1.21/SSEL0
(not available for LQFP80), P1.23/MISO0, P1.24/MOSI0-> Max SCK for master mode:
100Mhz / (2 x (0 + 1)) = 50Mhz-> Max SCK for slave mode: 100Mhz / 12 =
8.33Mhz*) SSP1 peripheral:-> Pins: P0.6/SSEL1, P0.7/SCK1, P0.8/MISO1,
P0.9/MOSI1-> Max SCK for master mode: 100Mhz / (2 x (0 + 1)) = 50Mhz-> Max SCK
for slave mode: 100Mhz / 12 = 8.33MhzNote that SPI and SSP0 has also mux-ed
pins. If you want to use all three of the SPI peripherals, you must use
different pins.
Regards,-daniel
--- On Thu, 1/20/11, Olivier Gautherot wrote:
From: Olivier Gautherot
Subject: Re: [lpc2000] Re: SPI buses on LPC1768
To: l...
Date: Thursday, January 20, 2011, 2:39 AM
Hi Scott,
On Wed, Jan 19, 2011 at 11:03 PM, Scott wrote:
No, there are separate sets of pins for SPI/SSP0/SSP1 even on the LQFP80
package. There are also three interrupt vectors and three sets of registers, so
the statement in the user manual doesn't appear to make sense. Can you try
it out?
-Scott
Unfortunately, I am still working on the schematics and hope to produce the
board during February so I won't have hardware for the next weeks. Does
anyone have a board to find out? I checked the Mbed board and it has only 2 SPI
ports so back to square 1 - this seems to support Paul's statement.
