> **
> Unfortunately the optimization of memcpy does not help. External memory
is
> no alternative for me. Since I have found a GPDMA configuration working
for
> 15MHz now, I am sticking to 15MHz MCICLK rate. This allows me to avoid
such
> big USB RAM buffer size - a 4*512 Byte big ring buffer in USB RAM is
enough
> to transfer up to 64*512 bytes per MCI. Speed is OK. Some cards do reach
> around 5MB/s.
>
> Even though it is working I am keen to get a better understanding of the
> GPDMA setting and its affects on the MCI.
>
> What makes me curious is the following behaviour:
> Target: LPC2388
> CPU CLK = 60MHz
>
> 1. Situation: MCICLK = 30MHz
>
> Working GPDMA Setting (GPDMA_CH0_CTRL):
>
> - TRANSFER_SIZE = 128 Bytes,
> - SRC_BURST_SIZE = 16,
> - DEST_BURST_SIZE = 16,
> - SRC_TRANS_WIDTH = 32bit,
> - DEST_TRANS_WIDTH= 32bit,
> - SRC_INCREMENT = ENABLE,
> - DEST_INCREMENT = DISABLE,
> - PROTECTION = DISABLE,
> - INT_ENABLE = ENABLE;
>
> 2. Situatuation: MCICLK = 15MHz
>
> Working GPDMA Setting (GPDMA_CH0_CTRL):
> Same setting as 1. Situation except: SRC_BURST_SIZE = 1,
>
> To be honest, I still do not know why those are the only settings
working
> for the two clock speeds. What is the impact of the MCI CLK on the Burst
> Size?
>
It's difficult to quess what settings make your system does not work,
but
please note that MCI settings must fit the DMA settings. For example; the
MCI fifo is 32 bit wide and if you change this in your DMA config
- SRC_TRANS_WIDTH = 32bit,
- DEST_TRANS_WIDTH= 32bit,
it may work wrong.
Unfortunately the optimization of memcpy does not help. External memory is no
alternative for me. Since I have found a GPDMA configuration working for 15MHz
now, I am sticking to 15MHz MCICLK rate. This allows me to avoid such big USB
RAM buffer size - a 4*512 Byte big ring buffer in USB RAM is enough to transfer
up to 64*512 bytes per MCI. Speed is OK. Some cards do reach around 5MB/s.
Even though it is working I am keen to get a better understanding of the GPDMA
setting and its affects on the MCI.
What makes me curious is the following behaviour:
Target: LPC2388
CPU CLK = 60MHz
Working GPDMA Setting (GPDMA_CH0_CTRL):
Same setting as 1. Situation except: SRC_BURST_SIZE = 1,
To be honest, I still do not know why those are the only settings working for
the two clock speeds. What is the impact of the MCI CLK on the Burst Size?
Can anyone give me a hint, where I can get some detailed information. LPC23xx
user manual does not help me to understand the issue.
Regards,
Heinz
Reply by ilovenxp●August 3, 20112011-08-03
Thanks again. After optimizing the copy function I can decrease my ring buffer
size (GPDMA linked list) down to 2*512 bytes. But to reach better speed, I
increased it to 4*512 bytes.
Even though it is working I am keen to get a better understanding of the GPDMA
setting and its affects on the MCI.
What makes me curious is the following behaviour:
Target: LPC2388
CPU CLK = 60MHz
Thanks for the answer. Now it makes more sense.
I am using a ring buffer to realize a packet transfer up to 127 * 512 bytes with
one WRITE_MULTI_BLCK SD-Command.
To update the DMA buffer sequencially I have to use memcpy(), because the USB
RAM is too small to store 127 * 512 bytes.
Unfortunately I have the problem, that memcpy does not keep up the speed, which
the GPDMA does.
If I want to send 16 * 512bytes I need at least a 10 * 512bytes USB RAM ring
buffer.
If I want to send 32 * 512bytes I need at least a 20 * 512bytes USB RAM ring
buffer.
I refill a free USB RAM buffer page (512 bytes) after each TC interrupt.
I tried to decrease the MCI clk from 30MHz to 15MHz but to decrease the transfer
speed, but by doing this a TxUnderrun Error Interrupt is thrown.
Do you have any idea how I could speed up copying the data from SRAM to USBRAM?
Or how I can decrease the DMA->MCI speed?
Hi
transfer size set to 128 does not mean that 128 bytes is going to be copied.
It means that 128*your_word_witdh bytes is going to be transfered. In your
case SRC_TRANS_WIDTH = 4 bytes and DEST_TRANS_WIDTH = 4 bytes so it is 512
bytes.
Regards,
Kuba
Reply by ilovenxp●August 1, 20112011-08-01
Hi everyone,
I got my "Memory -> DMA -> MCI" working with the following
setting:
MCI_DATA_CTRL:
DIRECTION = CONTROLLER_TO_CARD,
MODE = DATA_MODE_BLOCK,
BLK-Size = 512Bytes;
I got it working after playing around with the following settings:
GPDMA_CH0_CTRL (TRANSFER_SIZE, SRC_BURST_SIZE, DEST_BURST_SIZE, SRC_TRANS_WIDTH,
DEST_TRANS_WIDTH)
Still I do not get the logic behind. Even though I am using transfer
"TRANSFER_SIZE = 128 Bytes", it is still copying 512 bytes from the
linked list item buffer, before using the next one...
Can someone explain me this behaviour? What are the best settings for DMA/MCI
and why?
Thanks a lot and regards,
Heinz
Reply by Kuba Dorzak●March 14, 20112011-03-14
Thanks for the clues Paul. Indeed, my preliminary tests show that I can get
about 2.4MB/s for writing and 3.6MB/s for reading blocks.
Regards,
Kuba
Reply by Paul Curtis●February 21, 20112011-02-21
> The problem is that I have very slow transfers.
Approximately it's 100kB/s.
If you are writing single blocks only you will not write very quickly at
all.
? It's almost the same when using 1-bit mode without DMA.
Indeed. Single blocks are like that because of what the controller in the
card must do for them.
> ...so I assume that the average transfer should be
about 9MB/s with DMA and 4-bit mode.
It will be--for the data phase. However, you'll be hanging around
whilst
the card organizes the single block write for you and does all its
management. You will never achieve sustained 9MB/second.
