On 17 Jul 2006 08:29:16 -0500, in comp.arch.embedded
clubley@remove_me.eisner.decus.org-Earth.UFP (Simon Clubley) wrote:
>In article <44B8C167.EB507438@REMOVETHIS.hotmail.com>, Eeyore <rabbitsfriendsandrelations@REMOVETHIS.hotmail.com> writes:
>>
>>
>> Chris Hills wrote:
>>
>>> Is it just me (and Grant Edwards) or are the questions getting worse and
>>> pointless?
>>
>> It's the influence of google groups.
>>
>
>It's interesting that the most search queries on Google for both "embedded"
>and "google groups" (at the time of writing this) are coming from India.
>
>See:
>
>http://www.google.com/trends?q=embedded&ctab=0&geo=all&date=all
>http://www.google.com/trends?q=google+groups&ctab=0&geo=all&date=all
>
>However the number of queries for "google groups" compared to "embedded"
>are quite small:
>
>http://www.google.com/trends?q=embedded%2Cgoogle+groups&ctab=0&geo=all&date=all
>
>Simon.
>If Google's motto is "don't be evil", then how did we get Google Groups 2 ?
They should have started with "Do No Harm" motto
martin
Reply by Simon Clubley●July 17, 20062006-07-17
In article <44B8C167.EB507438@REMOVETHIS.hotmail.com>, Eeyore <rabbitsfriendsandrelations@REMOVETHIS.hotmail.com> writes:
>
>
> Chris Hills wrote:
>
>> Is it just me (and Grant Edwards) or are the questions getting worse and
>> pointless?
>
> It's the influence of google groups.
>
> Is it just me (and Grant Edwards) or are the questions getting worse and
> pointless?
It's the influence of google groups.
I liken many such posts to the level once exhibited by WebTVers.
Graham
Reply by Joseph●July 14, 20062006-07-14
Chris Hills wrote:
> In article <e95613$aki$1@cam-news1.cambridge.arm.com>, Joseph
> <joseph.yiu@somewhere-in-arm.com> writes
>
>>Peter Harrison wrote:
>>
>>
>>
>>>The OP asked a question that we must assume had some meaning and
>>>relevance to him. Granted, it was poorly phrased and possibly ambiguous.
>>>However, almost nobody seems to have tried answering the question and
>>>most seem to have almost willfully misinterpreted it. the original
>>>question asks about the need for 2 clocks per machine state in the 8051.
>>>A quick look at the Philips databook to remind me what an 8051 was (just
>>>kidding - stay calm) shows that a machine cycle consists of six machine
>>>states, each requiring 2 clocks. So all this stuff about 1, 2, 4, 6 and
>>>12 clock variants is a bit beside the point. If the OP really meant
>>>machine state (as written) rather than machine cycle (as read by most)
>>>then the question is probably quite fair. Certainly, a look at the
>>>Philips databook makes things a bit more clear. There is a small section
>>>specifically about CPU timing and Machine cycles. However, the family
>>>hardware guides most likely to be found by a less than thorough Google
>>>search don't always mention it. The 80C51 Family Architecture document
>>>found here:
>>>
>>>http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_
>>
>>1.pdf
>>
>>I guess the reason is the way the first generation of 8051 is designed.
>>(there wasn't VHDL/Verilog at that time, the chip layout was manually
>>created).
>>
>>At that time, registers could be implemented as latches.
>>So the first 8051 might have used "register" design that
>>required multiple clock phases to drive. For example,
>>1 flip-flop = 2 multiplexer latches in series
>>As a result, 2 clock cycles might be required to ensure correct
>>operation of the register.
>>And the design use 2 clock cycles for each machine state.
>
>
> At the time the 8051 was implemented they used 12 cycles.
> The 6, 4, 2 and 1 cycle have come about since VHDL/Verilog
>
>
The 12 cycles number is machine cycle.
Inside each machine cycle, it is divided into 6 states (S1-S6).
Each state takes 2 clock cycles (P1 and P2). I guess this is the
item that OP asked about.
Joseph
Reply by Chris Hills●July 14, 20062006-07-14
In article <e95613$aki$1@cam-news1.cambridge.arm.com>, Joseph
<joseph.yiu@somewhere-in-arm.com> writes
>Peter Harrison wrote:
>
>
>> The OP asked a question that we must assume had some meaning and
>> relevance to him. Granted, it was poorly phrased and possibly ambiguous.
>> However, almost nobody seems to have tried answering the question and
>> most seem to have almost willfully misinterpreted it. the original
>> question asks about the need for 2 clocks per machine state in the 8051.
>> A quick look at the Philips databook to remind me what an 8051 was (just
>> kidding - stay calm) shows that a machine cycle consists of six machine
>> states, each requiring 2 clocks. So all this stuff about 1, 2, 4, 6 and
>> 12 clock variants is a bit beside the point. If the OP really meant
>> machine state (as written) rather than machine cycle (as read by most)
>> then the question is probably quite fair. Certainly, a look at the
>> Philips databook makes things a bit more clear. There is a small section
>> specifically about CPU timing and Machine cycles. However, the family
>> hardware guides most likely to be found by a less than thorough Google
>> search don't always mention it. The 80C51 Family Architecture document
>> found here:
>>
>> http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_
>1.pdf
>>
>
>I guess the reason is the way the first generation of 8051 is designed.
>(there wasn't VHDL/Verilog at that time, the chip layout was manually
>created).
>
>At that time, registers could be implemented as latches.
>So the first 8051 might have used "register" design that
>required multiple clock phases to drive. For example,
>1 flip-flop = 2 multiplexer latches in series
>As a result, 2 clock cycles might be required to ensure correct
>operation of the register.
>And the design use 2 clock cycles for each machine state.
At the time the 8051 was implemented they used 12 cycles.
The 6, 4, 2 and 1 cycle have come about since VHDL/Verilog
--
\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
\/\/\/\/\ Chris Hills Staffs England /\/\/\/\/
/\/\/ chris@phaedsys.org www.phaedsys.org \/\/\
\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
Reply by ziggy●July 13, 20062006-07-13
In article <1152598467.894100.285310@m79g2000cwm.googlegroups.com>,
eerobert@gmail.com wrote:
> Why 8051 need 2 clock cycle for 1 system state?
Dont you mean 12 to 1?
And there is no magic, that is just how intel did it back then. Other
implementations have different clock/instruction ratios.
Reply by Joseph●July 13, 20062006-07-13
Peter Harrison wrote:
> The OP asked a question that we must assume had some meaning and
> relevance to him. Granted, it was poorly phrased and possibly ambiguous.
> However, almost nobody seems to have tried answering the question and
> most seem to have almost willfully misinterpreted it. the original
> question asks about the need for 2 clocks per machine state in the 8051.
> A quick look at the Philips databook to remind me what an 8051 was (just
> kidding - stay calm) shows that a machine cycle consists of six machine
> states, each requiring 2 clocks. So all this stuff about 1, 2, 4, 6 and
> 12 clock variants is a bit beside the point. If the OP really meant
> machine state (as written) rather than machine cycle (as read by most)
> then the question is probably quite fair. Certainly, a look at the
> Philips databook makes things a bit more clear. There is a small section
> specifically about CPU timing and Machine cycles. However, the family
> hardware guides most likely to be found by a less than thorough Google
> search don't always mention it. The 80C51 Family Architecture document
> found here:
>
> http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_1.pdf
>
I guess the reason is the way the first generation of 8051 is designed.
(there wasn't VHDL/Verilog at that time, the chip layout was manually
created).
At that time, registers could be implemented as latches.
So the first 8051 might have used "register" design that
required multiple clock phases to drive. For example,
1 flip-flop = 2 multiplexer latches in series
As a result, 2 clock cycles might be required to ensure correct
operation of the register.
And the design use 2 clock cycles for each machine state.
Joseph
Reply by Tom Lucas●July 13, 20062006-07-13
"Chris Hills" <chris@phaedsys.org> wrote in message
news:FAFzjHBgvVtEFACh@phaedsys.demon.co.uk...
> In article <1152703599.31886.0@iris.uk.clara.net>, Tom Lucas
> <news@REMOV
> EautoTOflameREPLY.clara.co.uk> writes
>>>>I think that it a bit insulting toward the OP -
>>>
>>> Not at all.
>>
>>It is not for me to be offended on behalf of anyone but it does imply
>>that the OP hasn't got the brains to understand the reply, rather than
>>the linguistic ability. However, if the OP is not offended then there
>>is
>>no problem.
>
> If the OP had enough intellect to understand the answer they would
> already have found the answer or framed the question differently. A
> search on google then a refined search would have got a lot of
> pointers
> as would the data sheet for the part concerned.
I had a search on google and I didn't find the answer, although I had no
problem understanding Peter Harrison's generous answer. You can't say
that the OP hadn't attempted to google for it because google won't yield
an answer without a lot of cajoling. I don't know what part he had but
not all datasheets are as helpful as others - perhaps the OP's was one
of the more vague.
> This would have lead to a very different question. As Others have
> commented the OP has not appeared to have done any preliminary work
> himself.
What are you basing this on? At first glance then it looks to be the
case but looking deeper then it has not proved to be and it's premature
to just dismiss it out of hand. However, if the OP really did do no
research then they should be ashamed - my point is that it is not
obvious whether they have or not.
> This is either laziness or lack of knowledge.
> If laziness then why should we answer?
> If lack of knowledge on how to find things on the Internet then they
> would lack the sort of mind that would handle the answer.
I'm aghast. That is _exactly_ the sort of elitism that rears its ugly
head far too often on this group. The OP may well have exhausted his
google talent searching but there is a fair level of skill and knowledge
required to post a usenet question, even with Google groups making it
more accessible. I used to work with a brilliant principle engineer who
designed what is regarded to be the greatest ever CRT deflection
amplifier but wouldn't have the first clue about how to post a question
to c.a.e.
As I've already said it is not clear whether the OP had searched or not,
and there main crime was a curt question. In lots of Far Eastern
cultures then there is no need for preamble and you can ask the question
right out. Whilst, it is possible that the OP is a local boy who should
know better, there is not nearly enough evidence to be as rude to them
as you have been.
When you reply to a question then your answers are normally well
considered and helpful but if you don't like someone's question then
simply don't repond to it, but please don't lambast the OP for their
lack of knowledge - we all have to start somewhere. I would rather see
lots of newbie questions going unanswered than one where the poster got
such a savaging that all other newbies are frightened to post. No-one is
paying by the byte anymore and it is hardly an effort to skip over the
posts you don't like until you find something you do.
<snip>
>>
>>There have been lots of ecellent replies but most what people have
>>actually said was that different instruction take different numbers of
>>clocks although Isaac alluded to microcode and Neil says he has a book
>>with the answer in it. Noone has actually given the reason why two
>>cycles are needed.
>
> Yes, that was answered, precisely and correctly. It is just that the
> OP
> did not understand the answer.
Where? By who? Only Peter Harrison's has hit the mark - all the others
skirted around it.
>> Granted there should be enough here for the OP to
>>have a renewed attack at google but I couldn't say that the question
>>had
>>been fully answered.
>
> "a renewed attack"? No evidence of a first attack. that is the point.
> As Grant (and the FAQ's) say we help those who show some sign of
> having
> put some effort in to it in the first place.
Well I've already discussed the google evidence. As for the FAQ, I asked
before without luck, but where is it? I have found a vxworks one and a
real time one but there doesn't appear to be a c.a.e FAQ. Perhaps it
would useful for Google groups to have a hyperlink to a group's FAQ when
you are in the group.
<snip>
>
> Yes. That many treat this NG (and others) as a low effort homework
> answering service.
I agree that that is a problem but I don't think the OP in this case was
doing homework - the question is too advanced for most students and is
highly unlikely to be covered in most courses these days.
Reply by Tom Lucas●July 13, 20062006-07-13
"Peter Harrison" <peter_harrison@ntlworld.com> wrote in message
news:mzetg.24802$1g.19925@newsfe1-win.ntli.net...
> Chris Hills wrote:
>> In article <1152649623.527310.218010@p79g2000cwp.googlegroups.com>,
>> Isaac Bosompem <x86asm@gmail.com> writes
>>> eerobert@gmail.com wrote:
>>>> Why 8051 need 2 clock cycle for 1 system state?
>>> I do not know what you mean by "system state". I only know that the
>>> 8051 by default takes 12 cycles for a machine state (I think that is
>>> what you meant).
>>
>> The original 8051 took 12 cycles. There are many 8051 cores that use
>> one of 12, 6, 4, 2 and 1 cycle per
>> clock. There are some 30-40 different cores out there using different
>> internal
>> design philosophies from traditional to soft cores fro ASICs. This
>> means
>> their internal timing is different.
>>
>> Some do run in 2 clock cycles per machine state.
>
> When I started with all this microprocessor malarkey, life seemed to
> be full of low-level machine architecture with much talk of things
> like fetch-execute cycles. By and large, many folk seem not to either
> want or need to know about these things, especially if all their
> development is done in a high level language. Not long ago I was
> sharing a moaning session with a university lecturer about how
> electronics students don't seem to have to know much at all about
> semiconductor junctions in order to get a degree. But I digress..
>
> The OP asked a question that we must assume had some meaning and
> relevance to him. Granted, it was poorly phrased and possibly
> ambiguous. However, almost nobody seems to have tried answering the
> question and most seem to have almost willfully misinterpreted it. the
> original question asks about the need for 2 clocks per machine state
> in the 8051. A quick look at the Philips databook to remind me what an
> 8051 was (just kidding - stay calm) shows that a machine cycle
> consists of six machine states, each requiring 2 clocks. So all this
> stuff about 1, 2, 4, 6 and 12 clock variants is a bit beside the
> point. If the OP really meant machine state (as written) rather than
> machine cycle (as read by most) then the question is probably quite
> fair. Certainly, a look at the Philips databook makes things a bit
> more clear. There is a small section specifically about CPU timing and
> Machine cycles. However, the family hardware guides most likely to be
> found by a less than thorough Google search don't always mention it.
> The 80C51 Family Architecture document found here:
>
> http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_1.pdf
>
> says what there is to say I think although it still falls short of
> explaining why two oscillator periods are required for each machine
> state.
>
> Sadly the most succinct answer posted so far is just as unhelpful - it
> was designed that way. All the actions appear to take place on the
> falling edge of the oscillator clock. using both edges would have
> taken a single clock per state but was presumably an expensive
> complication at the time the original 8051 was designed.
>
>
> Of course, the OP could have simply dropped a 1 and meant why 12
> clocks per machine cycle - who knows. We will never find out because
> he has probably been securely frightened away and should not cause any
> more embarrassment to himself or others.
>
> Pete Harrison
<original post deliberately reposted in full>
Thank you for that - I'd been interested to know the answer as well and,
whilst some of the posts here offered some help, this is the first to
provide a satisfactory answer for the OP.
Reply by Peter Harrison●July 12, 20062006-07-12
Chris Hills wrote:
> In article <1152649623.527310.218010@p79g2000cwp.googlegroups.com>,
> Isaac Bosompem <x86asm@gmail.com> writes
>> eerobert@gmail.com wrote:
>>> Why 8051 need 2 clock cycle for 1 system state?
>> I do not know what you mean by "system state". I only know that the
>> 8051 by default takes 12 cycles for a machine state (I think that is
>> what you meant).
>
> The original 8051 took 12 cycles.
>
> There are many 8051 cores that use one of 12, 6, 4, 2 and 1 cycle per
> clock.
>
> There are some 30-40 different cores out there using different internal
> design philosophies from traditional to soft cores fro ASICs. This means
> their internal timing is different.
>
> Some do run in 2 clock cycles per machine state.
>
>
>
When I started with all this microprocessor malarkey, life seemed to be
full of low-level machine architecture with much talk of things like
fetch-execute cycles. By and large, many folk seem not to either want or
need to know about these things, especially if all their development is
done in a high level language. Not long ago I was sharing a moaning
session with a university lecturer about how electronics students don't
seem to have to know much at all about semiconductor junctions in order
to get a degree. But I digress..
The OP asked a question that we must assume had some meaning and
relevance to him. Granted, it was poorly phrased and possibly ambiguous.
However, almost nobody seems to have tried answering the question and
most seem to have almost willfully misinterpreted it. the original
question asks about the need for 2 clocks per machine state in the 8051.
A quick look at the Philips databook to remind me what an 8051 was (just
kidding - stay calm) shows that a machine cycle consists of six machine
states, each requiring 2 clocks. So all this stuff about 1, 2, 4, 6 and
12 clock variants is a bit beside the point. If the OP really meant
machine state (as written) rather than machine cycle (as read by most)
then the question is probably quite fair. Certainly, a look at the
Philips databook makes things a bit more clear. There is a small section
specifically about CPU timing and Machine cycles. However, the family
hardware guides most likely to be found by a less than thorough Google
search don't always mention it. The 80C51 Family Architecture document
found here:
http://www.semiconductors.philips.com/acrobat_download/various/80C51_FAM_ARCH_1.pdf
says what there is to say I think although it still falls short of
explaining why two oscillator periods are required for each machine state.
Sadly the most succinct answer posted so far is just as unhelpful - it
was designed that way. All the actions appear to take place on the
falling edge of the oscillator clock. using both edges would have taken
a single clock per state but was presumably an expensive complication at
the time the original 8051 was designed.
Of course, the OP could have simply dropped a 1 and meant why 12 clocks
per machine cycle - who knows. We will never find out because he has
probably been securely frightened away and should not cause any more
embarrassment to himself or others.
Pete Harrison