An example to get you started. You also need to know the base address
of the registers (IMMR), and you probably have another header file out
there that defines the layout of registers and their offsets from the
base. That's probably defined in another part of the same header file
that defines the port bits.
So for a simple example that sets bit 9 or port D, you might have:
// Get the IMMR pointer (assuming the struct has "volatile"s)
mpc8xx_immr* immr = (mpc8xx_immr*)IMMR_BASE;
// Set up a mask (all of the PDDIR, PDPAR, and PDDAT are the same)
uint16 mask = PDDAT_D9;
// Should disable interrupts here - or use atomic bit routines
// Configure pin to be an OUTPUT pin
// (really only needs to be done once)
immr->pddir |= mask;
immr->pdpar &= ~mask;
// Set the bit
immr->pddat |= mask;
// Can reenable interrupts again
That portion of the header file that defines the bits is really
pretty useless. You can also just do something like:
#define PIN(p) (1 << (15-p))
...
mask = PIN(9);
If you're new to C *and* embedded systems, then you really need to
learn them FIRST before continuing. If you understand hardware and
embedded systems and are just vague on C, then mention that.
--
Darin Johnson
Reply by lear...@gmail.com●July 24, 20062006-07-24
Hey All,
I have a header file for MPC8xx freescale powerPC QUICC I uC (MPC885
specifically). I want to write a simple code to do a simple read write
for any of the INPUT/OUTPUT PORTs. I went through a documentation but I
dont know how to make use of the header file to make my job easier.
I am new to C/C++ so it will be great if someone can point me in the
right direction. May be a small snippet to show how to go ahead. Here
is part of the header code using port A. Thanks of any help....(not
looking for charity just help to get started)
/*-------------------------------------------------------------------------*
* INPUT/OUTPUT PORT
*
*-------------------------------------------------------------------------*/
/*-------------------------------------------------------*
* Port A Data Direction Register (PADIR) *
*-------------------------------------------------------*
* NOTE: For each DRx bit, the definition is as follows: *
* *
* 0 = The corrsponding bit is an input. *
* *
* 1 = The corresponding bit is an output. *
* *
* This register is cleared at system reset. *
*-------------------------------------------------------*/
#define PADIR_DR0 0x8000
#define PADIR_DR1 0x4000
#define PADIR_DR2 0x2000
#define PADIR_DR3 0x1000
#define PADIR_DR4 0x0800
#define PADIR_DR5 0x0400
#define PADIR_DR6 0x0200
#define PADIR_DR7 0x0100
#define PADIR_DR8 0x0080
#define PADIR_DR9 0x0040
#define PADIR_DR10 0x0020
#define PADIR_DR11 0x0010
#define PADIR_DR12 0x0008
#define PADIR_DR13 0x0004
#define PADIR_DR14 0x0002
#define PADIR_DD15 0x0001
/*----------------------------------------------------------------*
* Port A Pin Assignment Register (PAPAR) *
*----------------------------------------------------------------*
* NOTE: For each DDx bit, the definition is as follows: *
* *
* 0 = General-purpose I/O. The peripheral functions *
* of the pin are not used. *
* *
* 1 = Dedicated peripheral function. The pin is used *
* by the internal module. The on-chip peripheral *
* function to which it is dedicated can be determined *
* by other bits such as those in the PADIR. *
* *
* This register is cleared at system reset. *
*----------------------------------------------------------------*/
#define PAPAR_DD0 0x8000
#define PAPAR_DD1 0x4000
#define PAPAR_DD2 0x2000
#define PAPAR_DD3 0x1000
#define PAPAR_DD4 0x0800
#define PAPAR_DD5 0x0400
#define PAPAR_DD6 0x0200
#define PAPAR_DD7 0x0100
#define PAPAR_DD8 0x0080
#define PAPAR_DD9 0x0040
#define PAPAR_DD10 0x0020
#define PAPAR_DD11 0x0010
#define PAPAR_DD12 0x0008
#define PAPAR_DD13 0x0004
#define PAPAR_DD14 0x0002
#define PAPAR_DD15 0x0001
/*---------------------------------------------------------------*
* Port A Open Drain Register (PAODR) *
*---------------------------------------------------------------*
* NOTE: For each ODx bit, the definition is as follows: *
* *
* 0 = The I/O pin is actively driven as an output. *
* *
* 1 = The I/O pin is an open-drain driver. As an output, *
* the pin is actively driven low, otherwise it is *
* three-stated. *
* *
* This register is cleared at system reset. *
*---------------------------------------------------------------*/
#define PAODR_OD9 0x0040
#define PAODR_OD10 0x0020
#define PAODR_OD11 0x0010
#define PAODR_OD12 0x0008
#define PAODR_OD14 0x0002
/*--------------------------------------------*
* Port A Data Register (PADAT) *
*--------------------------------------------*
* NOTE: This register is undefined at reset. *
* See MPC860 User's Manual. *
*--------------------------------------------*/
#define PADAT_D0 0x8000
#define PADAT_D1 0x4000
#define PADAT_D2 0x2000
#define PADAT_D3 0x1000
#define PADAT_D4 0x0800
#define PADAT_D5 0x0400
#define PADAT_D6 0x0200
#define PADAT_D7 0x0100
#define PADAT_D8 0x0080
#define PADAT_D9 0x0040
#define PADAT_D10 0x0020
#define PADAT_D11 0x0010
#define PADAT_D12 0x0008
#define PADAT_D13 0x0004
#define PADAT_D14 0x0002
#define PADAT_D15 0x0001