VLSI Design
Special Issue on Networks-on-Chip
Call for Papers
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Single chip and embedded systems are becoming increasingly complex and
heterogeneous. Such systems-on-chip (SoCs) imply the seamless
integration of numerous IP cores performing different functions and
operating at different clock frequencies. On one hand, this integration
process requires standard interface sockets to allow for design reuse of
IP components across multiple platforms. On the other hand, it is
causing the scalability limitations of state-of-the-art SoC busses to
emerge.
Networks-on-chip (NoCs) are generally viewed as the ultimate solution
for the design of modular and scalable communication architectures, and
provide inherent support to the integration of heterogeneous cores
through the standardization of the network boundary. NoC architectures
loosen the delay bottleneck in signal propagation across deep-submicron
interconnects and are likely to improve design predictability, although
their area and power overheads still remain critical issues to be
addressed by research.
This special issue is dedicated to the aspects of architecture and
design methodology of on-chip interconnection systems and their
applications. Topics of interest include, but are not limited to:
* Design flows for NoCs and MP-SoC platforms
* Modeling, simulation, and test of NoC systems
* On-chip network monitoring and management
* Architectures and topologies
* Performance and trade-off analysis
* Mapping and scheduling applications/communication
* Energy efficiency and power management
* Fault tolerance and reliability issues
* Routing and addressing issues
* QoS in NoC systems
* Reconfigurability issues
* Industrial case studies of SoC designs using the NoC paradigm
Authors are encouraged to submit high-quality research contributions
that will not require major revisions.
Authors should follow the VLSI Design manuscript format described at
http://www.hindawi.com/GetJournal.aspx?journal=VLSI. Prospective authors
should submit an electronic copy of their complete manuscript through
the VLSI Design manuscript tracking system at
http://www.hindawi.com/mts/, according to the following timetable:
Manuscript Due October 15, 2006
Acceptance Notification December 15, 2006
Final Manuscript Due March 15, 2007
Publication Date 2nd Quarter, 2007
Guest Editors
--------------
Davide Bertozzi, Dipartimento di Ingegneria, Universit� di Ferrara, Italy
Shashi Kumar, Department of Electronics and Computer Engineering, School
of Engineering, J�nk�ping University, Sweden
Maurizio Palesi, Dipartimento di Ingegneria Informatica e delle
Telecomunicazioni, Universit� di Catania, Italy