> With many FPGAs having some kind of dual-port
BlockRAM, it is quite
> easy to have FIFOs to smooth out the processing. Still, trying to
> clock data into BlockRAM at 20 MHz takes a pretty fast FPGA.
The low-end Altera Cyclone series of devices, and Xilinx Spartan
devices all work fine at 100MHz or more. You just have to use the
RAM in synchronous (pipelined) mode (which is pretty much all
the newer devices support anyway).
--- In l..., "richas" wrote: >
> Thanks Paul, Olivier, and Dave. Hi again Dave ;-)
>
> I have, as Dave knows, already started pursuing the FPGA route. I think my
posting here is just a lean back into my comfort zone and I need to continue
with the FPGA. The FPGA + micro is intriguing, if it makes sense. It may speed
the design to have an external micro which could be later incorporated into the
FPGA.
>
> That packets out to the wifi would be a much slower rate than the adc sample
rate.
>
> I think, given that I am out of mental bandwidth, that I cannot deal with lack
of processing power. I just wanted a sanity check.
>
> Thanks guys.
>
> Rich
>
I haven't thought very much about the processing power requirement (I
don't know anything about the app) but the Analog Devices Blackfin uC runs
at 500 MHz and has DSP capabilities. The Sharc device is even faster and it,
too, has DSP.
For the FPGA approach, there are a number of small CPU cores available at
opencores.org. The T80 core (a full Z80) is one of my favorites. I added a
Compact Flash gadget to the bus and have CP/M 2.2 running with a full complement
of 16 logical drives of 8MB each. That's HUGE in Z80 terms. It also
provides a decent platform for readily available Z80 assemblers and C compilers.
Or Fortran and PL/I...
I suppose everyone else would want to use the MIPS core.
With many FPGAs having some kind of dual-port BlockRAM, it is quite easy to have
FIFOs to smooth out the processing. Still, trying to clock data into BlockRAM
at 20 MHz takes a pretty fast FPGA.
Richard
Reply by Olivier Gautherot●October 21, 20112011-10-21
Hi Rich,
On Fri, Oct 21, 2011 at 6:49 PM, richas wrote:
> **
> > How much slower, and what do you do with the data you don't want
from
> > the ADC? If you have to process the ADC data, then that processing
> > may determine how 'much' of an FPGA you need.
> > The two channels of analog data are IQ data and become a bit stream
> through, yet to be determined, processing. So it will take many ADC samples
> to produce one bit. One quick note about the bandwidth (from the User's Guide):
"12-bit conversion rate of 200 kHz"
Cheers
--
Olivier Gautherot
o...@gautherot.net http://www.linkedin.com/in/ogautherot
Reply by David Smead●October 21, 20112011-10-21
It can be done with an LPCxxxx processor.
DaveS
On Fri, Oct 21, 2011 at 1:37 PM, richas wrote:
> **
> I have a project that requires two 12-bit ADCs with parallel output and a
> sample rate of ~20-30 Msps. The micro will be processing the data into a
bit
> stream, formatting that into a data packet and sending it out via a canned
> wifi solution.
>
> I could use an FPGA instead of a micro but it would add a lot of cost and
> time to the project.
>
> I could just try it with an LPC1769, 120MHz, FIQ, for example but I assume
> there are methods to calculate the burden on the processor.
>
> What kind of pre-hardware analysis can be done to determine how much CPU
> time is required just to keep up with the parallel ADC inputs?
>
> Thanks
>
> Rich
>
>
>
Reply by richas●October 21, 20112011-10-21
> How much slower, and what do you do with the data you
don't want from
> the ADC? If you have to process the ADC data, then that processing
> may determine how 'much' of an FPGA you need.
>
The two channels of analog data are IQ data and become a bit stream through, yet
to be determined, processing. So it will take many ADC samples to produce one
bit.
> There's plenty of mental bandwidth on these
lists, but you need to
> specify the requirements well enough for others to offer their
> insight or experience.
Yes, but you are right, I have more work to do before, I try to tap the minds
here...
Thanks again
Rich
Reply by David Hawkins●October 21, 20112011-10-21
Hi Rich,
> That packets out to the wifi would be a much slower
rate than the adc sample rate.
How much slower, and what do you do with the data you don't want from
the ADC? If you have to process the ADC data, then that processing
may determine how 'much' of an FPGA you need.
If you only require bursts of samples, then use a FIFO, and the micro
can control the burst data capture.
> I think, given that I am out of mental bandwidth
There's plenty of mental bandwidth on these lists, but you need to
specify the requirements well enough for others to offer their
insight or experience.
Cheers,
Dave
Reply by richas●October 21, 20112011-10-21
Thanks Paul, Olivier, and Dave. Hi again Dave ;-)
I have, as Dave knows, already started pursuing the FPGA route. I think my
posting here is just a lean back into my comfort zone and I need to continue
with the FPGA. The FPGA + micro is intriguing, if it makes sense. It may speed
the design to have an external micro which could be later incorporated into the
FPGA.
That packets out to the wifi would be a much slower rate than the adc sample
rate.
I think, given that I am out of mental bandwidth, that I cannot deal with lack
of processing power. I just wanted a sanity check.
Thanks guys.
Rich
--- In l..., Paul Curtis wrote: > On 21 Oct 2011, at 21:37, richas wrote:
>
> > I have a project that requires two 12-bit ADCs with parallel output and a
sample rate of ~20-30 Msps. The micro will be processing the data into a bit
stream, formatting that into a data packet and sending it out via a canned wifi
solution.
> >
> > I could use an FPGA instead of a micro but it would add a lot of cost and
time to the project.
> >
> > I could just try it with an LPC1769, 120MHz, FIQ, for example but I assume
there are methods to calculate the burden on the processor.
> >
> > What kind of pre-hardware analysis can be done to determine how much CPU
time is required just to keep up with the parallel ADC inputs?
>
> Lower bound:
>
> 20Msps x 2 x 12 = 480 Mbps. What Wifi solution would you use for this data
stream? :-( That high speed USB. 802.11n is max 600mbps, and I see nowhere
near that with the equipment I have in my house.
>
> Let's say you want to read this using the CPU and not using DMA (which
just shifts the problem). Each dual sample is packed into a 32-bit word, you
need to deal with 20M 32-bit words per second. That means each 32 bit word has
a maximum of 120/20 = 6 instructions to read, process, and do something with.
What are you going to pack into those four instructions in the middle, assuming
that the read and write are single cycle?
>
> I would say that this minimum analysis shows that a 120MHz LPC1700 isn't
going to be up to the job, if I read what you want to do correctly.
>
> Well, unless I've made a complete arse of myself with a maths error.
>
> -- Paul.
>
Reply by Paul Curtis●October 21, 20112011-10-21
On 21 Oct 2011, at 21:37, richas wrote:
> I have a project that requires two 12-bit ADCs with
parallel output and a sample rate of ~20-30 Msps. The micro will be processing
the data into a bit stream, formatting that into a data packet and sending it
out via a canned wifi solution.
>
> I could use an FPGA instead of a micro but it would add a lot of cost and time
to the project.
>
> I could just try it with an LPC1769, 120MHz, FIQ, for example but I assume
there are methods to calculate the burden on the processor.
>
> What kind of pre-hardware analysis can be done to determine how much CPU time
is required just to keep up with the parallel ADC inputs?
Lower bound:
20Msps x 2 x 12 = 480 Mbps. What Wifi solution would you use for this data
stream? :-( That high speed USB. 802.11n is max 600mbps, and I see nowhere
near that with the equipment I have in my house.
Let's say you want to read this using the CPU and not using DMA (which just
shifts the problem). Each dual sample is packed into a 32-bit word, you need to
deal with 20M 32-bit words per second. That means each 32 bit word has a
maximum of 120/20 = 6 instructions to read, process, and do something with.
What are you going to pack into those four instructions in the middle, assuming
that the read and write are single cycle?
I would say that this minimum analysis shows that a 120MHz LPC1700 isn't
going to be up to the job, if I read what you want to do correctly.
Well, unless I've made a complete arse of myself with a maths error.
-- Paul.
Reply by Olivier Gautherot●October 21, 20112011-10-21
Hi Rich,
On Fri, Oct 21, 2011 at 5:37 PM, richas wrote:
> **
>
> I have a project that requires two 12-bit ADCs with parallel output and a
> sample rate of ~20-30 Msps. The micro will be processing the data into a
bit
> stream, formatting that into a data packet and sending it out via a canned
> wifi solution.
>
> I could use an FPGA instead of a micro but it would add a lot of cost and
> time to the project.
>
It sounds like a lot of data. 2 things:
- the LPC1769 won't keep up with this data rate
- what algorithm do you need to run?
If you evaluate the complexity and then multiply it by the data rate, you
will get an estimate of the MIPS that you actually need. The pure interrupts
will cause an overhead that won't keep up with your description...
FPGA/CPLD and a (very) fast converter are the way to go.
Continuing on from our discussion on the Altera forum ...
(though you have provided more info here)
> I have a project that requires two 12-bit ADCs with
parallel output and a sample rate of ~20-30 Msps. The micro will be processing
the data into a bit stream, formatting that into a data packet and sending it
out via a canned wifi solution.
>
> I could use an FPGA instead of a micro but it would add a lot of cost and time
to the project.
>
> I could just try it with an LPC1769, 120MHz, FIQ, for example but I assume
there are methods to calculate the burden on the processor.
>
> What kind of pre-hardware analysis can be done to determine how much CPU time
is required just to keep up with the parallel ADC inputs?
First you need to identify the specific WiFi component.
Then identify the data format required by the WiFi interface
for the data packets you are sending, eg., your ADC data will
consist of blocks of samples with header information.
I suspect your solution would need to involve both a processor
(for system initialization and header generation) and a CPLD,
or perhaps dual-port RAM between the ADC and the WiFi chip
so that you can stream data without it going through the
micro.
