On 30 Oct, in article
<d6ce4a6c.0410300858.4a756b75@posting.google.com>
toby@telegraphics.com.au "Toby Thain" wrote:
....
>Yes, that imprecision is also due to my misreading of the manual; I
>overlooked that Timer2 actually allows all divisors 2-16 (more
>familiar with the other timer modules that only have powers-of-2
>scales). You know how it is when you stare at something too long! :)
Reply by Spehro Pefhany●October 30, 20042004-10-30
On 30 Oct 2004 09:58:33 -0700, the renowned toby@telegraphics.com.au
(Toby Thain) wrote:
>Dan Henry <dhenry@sprynet.com> wrote in message news:<tmb6o0d6h8a3se80be3jrvdq4imtmhos3j@4ax.com>...
>> Dan Henry <dhenry@sprynet.com> wrote:
>>
>> >...
>> >Others have pointed out the postscale problem. For future reference,
>> >here's an Excel spreadsheet for working out those pre/post-scaler
>> >issues:
>> >
>> >http://dhenry.home.sprynet.com/pic_tmr2.xls
>>
>> Plus using that spreadsheet, you'll quickly discover that 1:16 pre/1:8
>> post with PR2 = 156 only gets you close to 500Hz and that 1:16/1:10
>> PR2 = 125 is spot-on.
>
>Yes, that imprecision is also due to my misreading of the manual; I
>overlooked that Timer2 actually allows all divisors 2-16 (more
>familiar with the other timer modules that only have powers-of-2
>scales). You know how it is when you stare at something too long! :)
>--T
The comments that indicate what you *wanted* the code to do can impede
troubleshooting. Maybe they should all left off 'til the end. ;-) ;-)
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Reply by Toby Thain●October 30, 20042004-10-30
Dan Henry <dhenry@sprynet.com> wrote in message news:<tmb6o0d6h8a3se80be3jrvdq4imtmhos3j@4ax.com>...
> Dan Henry <dhenry@sprynet.com> wrote:
>
> >...
> >Others have pointed out the postscale problem. For future reference,
> >here's an Excel spreadsheet for working out those pre/post-scaler
> >issues:
> >
> >http://dhenry.home.sprynet.com/pic_tmr2.xls
>
> Plus using that spreadsheet, you'll quickly discover that 1:16 pre/1:8
> post with PR2 = 156 only gets you close to 500Hz and that 1:16/1:10
> PR2 = 125 is spot-on.
Yes, that imprecision is also due to my misreading of the manual; I
overlooked that Timer2 actually allows all divisors 2-16 (more
familiar with the other timer modules that only have powers-of-2
scales). You know how it is when you stare at something too long! :)
--T
Reply by Dan Henry●October 30, 20042004-10-30
Dan Henry <dhenry@sprynet.com> wrote:
>toby@telegraphics.com.au (Toby Thain) wrote:
>
>>Hi,
>>
>>I'm seeing something unexpected in the running time of a Timer2 based
>>delay loop. With the combined prescale, period, and postscale, should
>>be setting TMR2IF at 500Hz? I expect the polling loop below to fall
>>out after approx 2ms. But it's taking closer to 3.8ms* and I can't
>>think of an explanation.
>>
>>Part is PIC18F6680, Fosc = 40 MHz.
>>
>>; THIS DOESN'T WORK...
>>; Timer2 input = Fosc/4 = 10,000,000 Hz
>>; divide by 1/16 prescale = 625,000 Hz
>>; divide by period (156) = ~4006 Hz
>>; divide by 1/8 postscale = ~500 Hz = approx 2ms!
>>delay2ms: ; set up Timer2
>> movlw b'01110010' ; 1:8 postscale,timer off,1:16 prescale
>> movwf T2CON
>> clrf TMR2
>> movlw 156 ; 156 x 8 x 16 cycles = ~1996.8us = approx 2ms
>> movwf PR2
>> bcf PIR1,TMR2IF
>> bsf T2CON,TMR2ON ; start it!
>> btfss PIR1,TMR2IF ; check for timer overflow
>> bra $-2
>> return
>>
>>*The running time is measured using Timer0, and I have confidence in
>>the correctness of that timer, having verified expected durations for
>>sanity with simple cycle wasting loops.
>
>Others have pointed out the postscale problem. For future reference,
>here's an Excel spreadsheet for working out those pre/post-scaler
>issues:
>
>http://dhenry.home.sprynet.com/pic_tmr2.xls
Plus using that spreadsheet, you'll quickly discover that 1:16 pre/1:8
post with PR2 = 156 only gets you close to 500Hz and that 1:16/1:10
PR2 = 125 is spot-on.
--
Dan Henry
Reply by Toby Thain●October 30, 20042004-10-30
Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote in message news:<dp75o01gunm95db0s2ioo4thm06fcmu6qv@4ax.com>...
> On 29 Oct 2004 19:06:15 GMT, the renowned garykato@aol.com (Gary Kato)
> wrote:
>
> >> movlw b'01110010' ; 1:8 postscale,timer off,1:16 prescale
> >>
> >
> >Your postscale bits are wrong.
>
> Yup. Specifically, you're getting 1:15 rather than 1:8.
Yes, I just found this out too. What a fool. Thanks! :-)
--T
>
>
> Best regards,
> Spehro Pefhany
Reply by Dan Henry●October 30, 20042004-10-30
toby@telegraphics.com.au (Toby Thain) wrote:
>Hi,
>
>I'm seeing something unexpected in the running time of a Timer2 based
>delay loop. With the combined prescale, period, and postscale, should
>be setting TMR2IF at 500Hz? I expect the polling loop below to fall
>out after approx 2ms. But it's taking closer to 3.8ms* and I can't
>think of an explanation.
>
>Part is PIC18F6680, Fosc = 40 MHz.
>
>; THIS DOESN'T WORK...
>; Timer2 input = Fosc/4 = 10,000,000 Hz
>; divide by 1/16 prescale = 625,000 Hz
>; divide by period (156) = ~4006 Hz
>; divide by 1/8 postscale = ~500 Hz = approx 2ms!
>delay2ms: ; set up Timer2
> movlw b'01110010' ; 1:8 postscale,timer off,1:16 prescale
> movwf T2CON
> clrf TMR2
> movlw 156 ; 156 x 8 x 16 cycles = ~1996.8us = approx 2ms
> movwf PR2
> bcf PIR1,TMR2IF
> bsf T2CON,TMR2ON ; start it!
> btfss PIR1,TMR2IF ; check for timer overflow
> bra $-2
> return
>
>*The running time is measured using Timer0, and I have confidence in
>the correctness of that timer, having verified expected durations for
>sanity with simple cycle wasting loops.
Others have pointed out the postscale problem. For future reference,
here's an Excel spreadsheet for working out those pre/post-scaler
issues:
http://dhenry.home.sprynet.com/pic_tmr2.xls
--
Dan Henry
Reply by Spehro Pefhany●October 29, 20042004-10-29
On 29 Oct 2004 19:06:15 GMT, the renowned garykato@aol.com (Gary Kato)
wrote:
Yup. Specifically, you're getting 1:15 rather than 1:8.
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Hi,
I'm seeing something unexpected in the running time of a Timer2 based
delay loop. With the combined prescale, period, and postscale, should
be setting TMR2IF at 500Hz? I expect the polling loop below to fall
out after approx 2ms. But it's taking closer to 3.8ms* and I can't
think of an explanation.
Part is PIC18F6680, Fosc = 40 MHz.
; THIS DOESN'T WORK...
; Timer2 input = Fosc/4 = 10,000,000 Hz
; divide by 1/16 prescale = 625,000 Hz
; divide by period (156) = ~4006 Hz
; divide by 1/8 postscale = ~500 Hz = approx 2ms!
delay2ms: ; set up Timer2
movlw b'01110010' ; 1:8 postscale,timer off,1:16 prescale
movwf T2CON
clrf TMR2
movlw 156 ; 156 x 8 x 16 cycles = ~1996.8us = approx 2ms
movwf PR2
bcf PIR1,TMR2IF
bsf T2CON,TMR2ON ; start it!
btfss PIR1,TMR2IF ; check for timer overflow
bra $-2
return
*The running time is measured using Timer0, and I have confidence in
the correctness of that timer, having verified expected durations for
sanity with simple cycle wasting loops.