I would like to exchange information on the Xilinx VSK with others
using the kit.

In particular I have the following observations:

A1. The VSK provides no help to people who do not wish to invest in (a)
Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible
with 8.1. VSK assumes that anyone buying VSK will also buy these
packages, or has them already.

A2. Xilinx should state the conditions in A1 clearly where it offers
VSK for sale.

A3. There is one other serious flaw in the VSK and in the VIOBUS in
that they do not allow for the video clock in the VIODC to be passed
down to ML402 --- so far as I understand the documentation. Only the
100 MHz ML402 clock can be passed up to the VIODC. This situation is
not conducive for testing video designs.

A4. Ideally, Xilinx should have sold the VSK with the following

    A4.1. Verilog and VHDL code for the VIODC (Video I/O Daughter Card)
to perform the setup for the video encoder and decoder chips.

    A4.2. Provision for passing the pixel clock from VIODC to ML402.

    A4.3. Some minimal Verilog and VHDL code for the ML402 including a
pass-through module. A user could then replace the pass-through module
with his/her code in a few minutes and have had a fully functional test
system.

As things stand, I think the VSK is quite useless for my purposes.

I am eager to hear from other users.

Arun Kumar