The SSP1 exist only in the /01 version

The SSP0 block is identical for all LPC13xx parts. The SSP1 block is available on part LPC1313FBD48/01 only.

Alex

On 05/19/2012 10:29 AM, Martin Cibulski wrote:

> Hello,
>
> please, I need help for using the second SSP controller (SSP1)
> on the LPC1313 part in master mode.
>
> I programmed the initialization like described in the
> datasheet, try to send test data, but nothing appears on the outputs.
>
> I checked with a logic analyser and in software mode everything
> works fine. But when I use the hardware SSP, nothing happens.
>
> Is there anything wrong with the second SSP controller
> on the LPC1313 ?
>
> Here is my test routine, it should send 0xAA and 0x55,
> wait between frames. I checked the the wait loop
> has not been optimized away.
>
> may be I forgot something trivial ... ?
>
> Thank you for help,
> Martin Cibulski
>
> BOOL ssp1_init_master (void)
> {
> int i;
> int nDummy;
>
> LPC_SYSCON->PRESETCTRL |= (0x01 << 2); // Reset for SSP1
> off
> LPC_SYSCON->SYSAHBCLKCTRL |= (0x01 << 18); // Clock for SSP1 on
> LPC_SYSCON->SSP1CLKDIV = 2; // Clock divider > 1
>
> LPC_IOCON->PIO2_0 &= ~0x07; // SSEL1
> LPC_IOCON->PIO2_0 |= 0x02; // SSEL1
> LPC_GPIO2->DIR |= (0x01 << 0); // Output
>
> LPC_IOCON->PIO2_1 &= ~0x07; // SCK1
> LPC_IOCON->PIO2_1 |= 0x02; // SCK1
> LPC_GPIO2->DIR |= (0x01 << 1); // Output
>
> LPC_IOCON->PIO2_3 &= ~0x07; // MOSI1
> LPC_IOCON->PIO2_3 |= 0x02; // MOSI1
> LPC_GPIO2->DIR |= (0x01 << 3); // Output
>
> LPC_IOCON->PIO2_2 &= ~0x02; // MISO1
> LPC_IOCON->PIO2_2 |= 0x02; // MISO1
> LPC_GPIO2->DIR &= ~(0x01 << 2); // Output
>
> LPC_SSP1->CR1 = 0x00 << 1; // SSP Disable
> LPC_SSP1->CR1 = 0x01 << 1; // SSP Enable
> LPC_SSP1->CR0 = (0x07 << 0) // 8 bit
> Transfer
> | (0x00 << 4) // SPI Frames
> | (0x01 << 6) // CLK high
> between frames
> | (0x01 << 7) // Clock Out
> Phase 2
> | (0x10 << 8); // Serial Clock rate
> LPC_SSP1->CPSR = 2;
>
> while (1) {
> LPC_SSP1->DR = 0xAA; // Send data
> for (i=0; i<10000; i++);
> LPC_SSP1->DR = 0x55; // Send data
> for (i=0; i<10000; i++);
> }

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Hello,

please, I need help for using the second SSP controller (SSP1)
on the LPC1313 part in master mode.

I programmed the initialization like described in the
datasheet, try to send test data, but nothing appears on the outputs.

I checked with a logic analyser and in software mode everything
works fine. But when I use the hardware SSP, nothing happens.

Is there anything wrong with the second SSP controller
on the LPC1313 ?

Here is my test routine, it should send 0xAA and 0x55,
wait between frames. I checked the the wait loop
has not been optimized away.

may be I forgot something trivial ... ?

Thank you for help,
Martin Cibulski
BOOL ssp1_init_master (void)
{
int i;
int nDummy;

LPC_SYSCON->PRESETCTRL |= (0x01 << 2); // Reset for SSP1
off
LPC_SYSCON->SYSAHBCLKCTRL |= (0x01 << 18); // Clock for SSP1 on
LPC_SYSCON->SSP1CLKDIV = 2; // Clock divider 1
LPC_IOCON->PIO2_0 &= ~0x07; // SSEL1
LPC_IOCON->PIO2_0 |= 0x02; // SSEL1
LPC_GPIO2->DIR |= (0x01 << 0); // Output

LPC_IOCON->PIO2_1 &= ~0x07; // SCK1
LPC_IOCON->PIO2_1 |= 0x02; // SCK1
LPC_GPIO2->DIR |= (0x01 << 1); // Output

LPC_IOCON->PIO2_3 &= ~0x07; // MOSI1
LPC_IOCON->PIO2_3 |= 0x02; // MOSI1
LPC_GPIO2->DIR |= (0x01 << 3); // Output

LPC_IOCON->PIO2_2 &= ~0x02; // MISO1
LPC_IOCON->PIO2_2 |= 0x02; // MISO1
LPC_GPIO2->DIR &= ~(0x01 << 2); // Output

LPC_SSP1->CR1 = 0x00 << 1; // SSP Disable
LPC_SSP1->CR1 = 0x01 << 1; // SSP Enable
LPC_SSP1->CR0 = (0x07 << 0) // 8 bit
Transfer
| (0x00 << 4) // SPI Frames
| (0x01 << 6) // CLK high
between frames
| (0x01 << 7) // Clock Out
Phase 2
| (0x10 << 8); // Serial Clock rate
LPC_SSP1->CPSR = 2;

while (1) {
LPC_SSP1->DR = 0xAA; // Send data
for (i=0; i<10000; i++);
LPC_SSP1->DR = 0x55; // Send data
for (i=0; i<10000; i++);
}

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