Reply by "M. Manca" ●May 28, 20122012-05-28
Il 28/05/2012 11:29, amr_mt_bekhit ha scritto:
>
>
> According to the LPC1788 datasheet in section 11.6 SSP interface, the
> minimum clock period when operating in master mode is 30ns, giving a
> maximum frequency of 33MHz.
>
The data are related to SSP working in SPI mode.
More generally for 178x parts SSP maximum rate is 60Mbit/s in SSP master
mode and 10Mbit/s in SSP slave mode.
> Amr
>
> --- In l... ,
> Alexan_e wrote:
> >
> > There was a question in Keil forum about the max SPI speed that
> could be
> > achieved using SSP in LPC1788 and a core clock of 120Mhz and based on
> > the user manual the max speed for the SSP peripheral is core_clock/2
> > which gives 60MHz.
> >
> > Assuming that the PCB is designed to work fine with this speed, is this
> > achievable from the MCU side?
> > Is it possible for the output stage of the LPC to switch at such a high
> > speed?
> >
> > I also found a link in NXP support
> > http://ics.nxp.com/support/faq/microcontrollers/lpc17xx/peripherals/
> > which is for LPc175x/6x that has max cpu clock or 100MHz and the
> text says
> > *
> > *
> > *Q:
> > * * What is the maximum SSP speed on the LPC17xx?*
> > *A:*
> > The maximum SSP speed (in master mode) is pclk/2. The maximum clock
> > (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral
> > clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode)
> > will be 50 Mbit/sec (100MHz/2).
> >
> >
> >
> > Are the mentioned speeds achievable?
> >
> > Alex
> >



An Engineer's Guide to the LPC2100 Series

Reply by Alexan_e ●May 28, 20122012-05-28
I guess the meaning is min clock frequency you can use and typical
frequency you can use although the values are given in as a period time.

Alex
On 05/28/2012 01:04 PM, Phil Young wrote:
>
> That doesn't seem to make sense
>
> If the MIN period is 30nS then the typical can't be 25nS.
>
> Phil.
>
> From: l...
> [mailto:l... ] On
> Behalf Of
> Alexan_e
> Sent: 28 May 2012 10:46
> To: l...
> Subject: Re: [lpc2000] Re: SSP max transfer rate for LPC17xx
>
> I didn't think of looking there for the specs, thank you for pointing that
> out.
>
> According to that dynamic characteristic table the SSP clock in master
> mode
> can have a min period of 30ns (33MHz) and typical 25ns (40Mhz).
>
> So I guess that is the absolute max although probably still not achievable
> when you take into account the rest of the timing parameters.
>
> Alex
>
> On 05/28/2012 12:29 PM, amr_mt_bekhit wrote:
>
> >
> >
> > According to the LPC1788 datasheet in section 11.6 SSP interface, the
> > minimum clock period when operating in master mode is 30ns, giving a
> > maximum frequency of 33MHz.
> >
> > Amr
> >
> > --- In l...
>
> ,
> > Alexan_e wrote:
> > >
> > > There was a question in Keil forum about the max SPI speed that
> > could be
> > > achieved using SSP in LPC1788 and a core clock of 120Mhz and based on
> > > the user manual the max speed for the SSP peripheral is core_clock/2
> > > which gives 60MHz.
> > >
> > > Assuming that the PCB is designed to work fine with this speed, is
> this
> > > achievable from the MCU side?
> > > Is it possible for the output stage of the LPC to switch at such a
> high
> > > speed?
> > >
> > > I also found a link in NXP support
> > > http://ics.nxp.com/support/faq/microcontrollers/lpc17xx/peripherals/
> > > which is for LPc175x/6x that has max cpu clock or 100MHz and the
> > text says
> > > *
> > > *
> > > *Q:
> > > * * What is the maximum SSP speed on the LPC17xx?*
> > > *A:*
> > > The maximum SSP speed (in master mode) is pclk/2. The maximum clock
> > > (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral
> > > clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode)
> > > will be 50 Mbit/sec (100MHz/2).
> > >
> > >
> > >
> > > Are the mentioned speeds achievable?
> > >
> > > Alex
> > >
> >
--
Alex
---------------------
http://alexan.edaboard.eu/ (Home of ARMwizard, a free tool for peripheral initialization of LPC2xxx/17xx/13xx/11xx microcontrollers )

Reply by Phil Young ●May 28, 20122012-05-28
That doesn't seem to make sense

If the MIN period is 30nS then the typical can't be 25nS.

Phil.

From: l... [mailto:l...] On Behalf Of
Alexan_e
Sent: 28 May 2012 10:46
To: l...
Subject: Re: [lpc2000] Re: SSP max transfer rate for LPC17xx

I didn't think of looking there for the specs, thank you for pointing that
out.

According to that dynamic characteristic table the SSP clock in master mode
can have a min period of 30ns (33MHz) and typical 25ns (40Mhz).

So I guess that is the absolute max although probably still not achievable
when you take into account the rest of the timing parameters.

Alex

On 05/28/2012 12:29 PM, amr_mt_bekhit wrote:

> According to the LPC1788 datasheet in section 11.6 SSP interface, the
> minimum clock period when operating in master mode is 30ns, giving a
> maximum frequency of 33MHz.
>
> Amr
>
> --- In l...
,
> Alexan_e wrote:
> >
> > There was a question in Keil forum about the max SPI speed that
> could be
> > achieved using SSP in LPC1788 and a core clock of 120Mhz and based on
> > the user manual the max speed for the SSP peripheral is core_clock/2
> > which gives 60MHz.
> >
> > Assuming that the PCB is designed to work fine with this speed, is this
> > achievable from the MCU side?
> > Is it possible for the output stage of the LPC to switch at such a high
> > speed?
> >
> > I also found a link in NXP support
> > http://ics.nxp.com/support/faq/microcontrollers/lpc17xx/peripherals/
> > which is for LPc175x/6x that has max cpu clock or 100MHz and the
> text says
> > *
> > *
> > *Q:
> > * * What is the maximum SSP speed on the LPC17xx?*
> > *A:*
> > The maximum SSP speed (in master mode) is pclk/2. The maximum clock
> > (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral
> > clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode)
> > will be 50 Mbit/sec (100MHz/2).
> >
> >
> >
> > Are the mentioned speeds achievable?
> >
> > Alex
>



Reply by Alexan_e ●May 28, 20122012-05-28
I didn't think of looking there for the specs, thank you for pointing that out.

According to that dynamic characteristic table the SSP clock in master mode can have a min period of 30ns (33MHz) and typical 25ns (40Mhz).

So I guess that is the absolute max although probably still not achievable when you take into account the rest of the timing parameters.

Alex
On 05/28/2012 12:29 PM, amr_mt_bekhit wrote:

> According to the LPC1788 datasheet in section 11.6 SSP interface, the
> minimum clock period when operating in master mode is 30ns, giving a
> maximum frequency of 33MHz.
>
> Amr
>
> --- In l... ,
> Alexan_e wrote:
> >
> > There was a question in Keil forum about the max SPI speed that
> could be
> > achieved using SSP in LPC1788 and a core clock of 120Mhz and based on
> > the user manual the max speed for the SSP peripheral is core_clock/2
> > which gives 60MHz.
> >
> > Assuming that the PCB is designed to work fine with this speed, is this
> > achievable from the MCU side?
> > Is it possible for the output stage of the LPC to switch at such a high
> > speed?
> >
> > I also found a link in NXP support
> > http://ics.nxp.com/support/faq/microcontrollers/lpc17xx/peripherals/
> > which is for LPc175x/6x that has max cpu clock or 100MHz and the
> text says
> > *
> > *
> > *Q:
> > * * What is the maximum SSP speed on the LPC17xx?*
> > *A:*
> > The maximum SSP speed (in master mode) is pclk/2. The maximum clock
> > (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral
> > clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode)
> > will be 50 Mbit/sec (100MHz/2).
> >
> >
> >
> > Are the mentioned speeds achievable?
> >
> > Alex
>
Reply by amr_mt_bekhit ●May 28, 20122012-05-28
According to the LPC1788 datasheet in section 11.6 SSP interface, the minimum clock period when operating in master mode is 30ns, giving a maximum frequency of 33MHz.

Amr

--- In l..., Alexan_e wrote:
>
> There was a question in Keil forum about the max SPI speed that could be
> achieved using SSP in LPC1788 and a core clock of 120Mhz and based on
> the user manual the max speed for the SSP peripheral is core_clock/2
> which gives 60MHz.
>
> Assuming that the PCB is designed to work fine with this speed, is this
> achievable from the MCU side?
> Is it possible for the output stage of the LPC to switch at such a high
> speed?
>
> I also found a link in NXP support
> http://ics.nxp.com/support/faq/microcontrollers/lpc17xx/peripherals/
> which is for LPc175x/6x that has max cpu clock or 100MHz and the text says
> *
> *
> *Q:
> * * What is the maximum SSP speed on the LPC17xx?*
> *A:*
> The maximum SSP speed (in master mode) is pclk/2. The maximum clock
> (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral
> clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode)
> will be 50 Mbit/sec (100MHz/2).
>
> Are the mentioned speeds achievable?
>
> Alex
>

Reply by Alexan_e ●May 28, 20122012-05-28
There was a question in Keil forum about the max SPI speed that could be
achieved using SSP in LPC1788 and a core clock of 120Mhz and based on
the user manual the max speed for the SSP peripheral is core_clock/2
which gives 60MHz.

Assuming that the PCB is designed to work fine with this speed, is this
achievable from the MCU side?
Is it possible for the output stage of the LPC to switch at such a high
speed?

I also found a link in NXP support
http://ics.nxp.com/support/faq/microcontrollers/lpc17xx/peripherals/
which is for LPc175x/6x that has max cpu clock or 100MHz and the text says
*
*
*Q:
* * What is the maximum SSP speed on the LPC17xx?*
*A:*
The maximum SSP speed (in master mode) is pclk/2. The maximum clock
(CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral
clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode)
will be 50 Mbit/sec (100MHz/2).

Are the mentioned speeds achievable?

Alex