> Hans-Bernhard Broeker wrote:
 >
 >>Steven P <photodose@gmx.de> wrote:
 >>
 >>
 >>>I have a project using a 32bits little endian processor but with only
 >>>16 bits data bus. How will it behave when it puts data on the data bus.
 >>>also in little endian mode?
 >>
 >>Like the datasheet says it does.  Given you didn't bother telling
 >>anyeone what that 32bit processor actually is, that's the only
 >>possible answer.
 >>
 >>--
 >>Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
 >>Even if all the snow were burnt, ashes would remain.
 >
 >

Steven P wrote:
> It is a ethernet chip from SMSC, LAN91C111.  I have thought it can be
> answered generally in broad sense just like endianess in memory.

The 91C111 is not a processor, as seen from the bus. It runs
as a bus slave, not master.

The chip runs perfectly well in 16 bit mode. Actually, the
internal registers on the chip are 16 bits in size.

The byte/halfword/fullword accesses are governed by the low
address bits (A1 to A3) and the byte enable controls (BE0- to BE3-).
For details, please read the data sheet.

The 16 bit data bus is connected so that the least significant
bit goes to D0 and the most significant bit goes to D15.

---

In my experience, initializing the MII properly is the most
difficult part in getting this chip work.

HTH

-- 

Tauno Voipio
tauno voipio (at) iki fi

On 1 Oct 2006 06:18:58 -0700, "Steven P" <photodose@gmx.de> wrote:

>It is a ethernet chip from SMSC, LAN91C111.  I have thought it can be
>answered generally in broad sense just like endianess in memory.

You should really read the data sheet carefully.

Some chips might only support byte access, so you would have to do
multiple byte read/writes to read a 16 bit register.

Other devices may require that 16 bit read/writes (using 16 bit short
int reference in most cases) to be used, 8 or 32 bit access is not
possible. The access must go to an even address regardless if the
actual register is 8 or 16 bits wide or if the 8 bit register of
interest is in the even or odd address. The CPU endiannes dictates how
the 8 bit bytes will end up in your 16/32 bit CPU register. 

Note that with peripherals requiring 16 bit access, when there are two
unrelated 8 bit registers in an aligned 16 bit word, you must prepare
correct values for _both_ peripheral registers (within your CPU
register), before performing the 16 bit write to these two 8 bit
peripheral registers, even if you actually plan to modify only the
other.

Paul

Steven P wrote:

> I have a project using a 32bits little endian processor but with only
> 16 bits data bus. How will it behave when it puts data on the data bus.
> also in little endian mode? And if the data type has length longer than
> the IO Data bus, how will it normally behave? Does endianness only
> relate to memory?

No.  Endianness also relates to byte order in serial transmission.

> Example.  short int a = 0x2211, will it puts data with the same order
> on data[15:00], i.e. D[7:0] = 0x11 and D[15:8]= 0x22, or with exchanged
> order?

Most processors number the bit lines from 0 being the lsb, through the 
largest for the msb.  Assuming that is true of your processor, your 
proposed mapping is correct.  Endianness is not an issue for a single word.

> How about a long int a =0x44332211, what will it put on the data bus? (
> it seems to me it is compiler dependent)

Since it only has a 16-bit I/O bus, the bits placed on the bus are the 
16 bits written to the I/O port.  If you write the 16 least significant 
bits, that's what will appear on the bus.  If you write 32 bits as two 
16-bit transfers, it depends on what order you write the 16-bit groups. 
  If you use DMA with ascending address, then the 16-bit groups would be 
written in memory-address order.

-- 
Thad

Steven P wrote:
> Hans-Bernhard Broeker wrote:
>> Steven P <photodose@gmx.de> wrote:
>>
>>> I have a project using a 32bits little endian processor but with
>>> only 16 bits data bus. How will it behave when it puts data on
>>> the data bus. also in little endian mode?
>>
>> Like the datasheet says it does.  Given you didn't bother telling
>> anyeone what that 32bit processor actually is, that's the only
>> possible answer.
> 
> It is a ethernet chip from SMSC, LAN91C111.  I have thought it can
> be answered generally in broad sense just like endianess in memory.

Nor can the memory endianess be resolved in a word.  How many ways
can you arrange the 4 octets of a 32 bit word (assuming 8 bit
bytes).  In actuallity only 2 of those possibilities are most
likely, but more do occur.  Read your data sheets.

-- 
 Some informative links:
   <news:news.announce.newusers
   <http://www.geocities.com/nnqweb/>
   <http://www.catb.org/~esr/faqs/smart-questions.html>
   <http://www.caliburn.nl/topposting.html>
   <http://www.netmeister.org/news/learn2quote.html>
   <http://cfaj.freeshell.org/google/>

Thanks for your opinion. I found the answer in another application
notes of smsc. It requires byte swap when connecting to a big endian
cpu. 


Steven

Steven P wrote:

> Good Morning:
> 
> I have a project using a 32bits little endian processor but with only
> 16 bits data bus. How will it behave when it puts data on the data bus.
> also in little endian mode? And if the data type has length longer than
> the IO Data bus, how will it normally behave? Does endianness only
> relate to memory?
> 
> Example.  short int a = 0x2211, will it puts data with the same order
> on data[15:00], i.e. D[7:0] = 0x11 and D[15:8]= 0x22, or with exchanged
> order?
> 
> How about a long int a =0x44332211, what will it put on the data bus? (
> it seems to me it is compiler dependent)

It is not the memory that has an endian. Try swapping the
datalines on memory, try swapping the adresslines on
(static-) memory. It is solely the processor that has an
endian-ness. I/O tends to be little endian, low byte on low
adress. Beside that most IO is 8bit anyway.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

It is a ethernet chip from SMSC, LAN91C111.  I have thought it can be
answered generally in broad sense just like endianess in memory.


Steven



Hans-Bernhard Broeker wrote:
> Steven P <photodose@gmx.de> wrote:
>
> > I have a project using a 32bits little endian processor but with only
> > 16 bits data bus. How will it behave when it puts data on the data bus.
> > also in little endian mode?
>
> Like the datasheet says it does.  Given you didn't bother telling
> anyeone what that 32bit processor actually is, that's the only
> possible answer.
>
> --
> Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
> Even if all the snow were burnt, ashes would remain.

Steven P <photodose@gmx.de> wrote:

> I have a project using a 32bits little endian processor but with only
> 16 bits data bus. How will it behave when it puts data on the data bus.
> also in little endian mode? 

Like the datasheet says it does.  Given you didn't bother telling
anyeone what that 32bit processor actually is, that's the only
possible answer.

-- 
Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.

Good Morning:

I have a project using a 32bits little endian processor but with only
16 bits data bus. How will it behave when it puts data on the data bus.
also in little endian mode? And if the data type has length longer than
the IO Data bus, how will it normally behave? Does endianness only
relate to memory?

Example.  short int a = 0x2211, will it puts data with the same order
on data[15:00], i.e. D[7:0] = 0x11 and D[15:8]= 0x22, or with exchanged
order?

How about a long int a =0x44332211, what will it put on the data bus? (
it seems to me it is compiler dependent)

Thanks in advance

Steven