Very cool, thank you. I just checked the PCLKSEL0 configuration value in
"system_LPC17xx.c" under CMSIS2p00_LPC17xx and it's default value is zero.
NXP was nice enough to comment each bits function towards the top as follows:
PCLK_TIMER0: Peripheral Clock Selection for TIMER0
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
So, since PCLKSEL0 is defaulted to all zeros that means the PCLK is running a
Cclk/4 or 100MHz/4 => 25MHz
Let me see if I can calculate each one:
#define TIMER0_INTERVAL ((2 * (4 *(SystemCoreClock/10))) - 1)
=> 80x10^6 / 25MHz => 3.2 seconds
#define TIMER0_INTERVAL ((2 *(4 *(SystemCoreClock/10))/3) - 1)
=> 26.667x190^6 / 25MHz => 1.067 or ~ 1 second
#define TIMER0_INTERVAL ((2 *(4 *(SystemCoreClock/10))/5) - 1)
=> 16x10^6 / 25MHz => 640ms
#define TIMER0_INTERVAL ((2 *(4 *(SystemCoreClock/10))/7) - 1)
=> 11.429 x 10^6 / 25MHz => .457 seconds
From my understand you really don't need the 2*4* system core clock since
it is just a play on numbers and you can just enter a value that works. For
instance to get 1 second all you have to do is define "TIMER0_INTERVAL" to 25
million and to get .5 seconds you need 12.5 million.
Did I get this right? And again, thank you for the reply and taking the time to
help me understand this.
--- In l..., Felipe de Andrade Neves Lavratti wrote:
>
> LPC_TIM0->TC counts each clock cycle of the peripheral. Usually this clock
> is set to be 1/4 of the SystemCoreClock.
> LPC_TIM0->MR0 is a match register, each time TC == MR0 something can
> happen: a TC reset, an Interrupt, or both. This setup is made on one of the
> LPC_TIM0 registers.
> Lets suppose the TIMER0 clock is 10Mhz, and you configure the MR0 with the
> number 10000000 - 1;
> If you set the MR0 with this number, and configure the timer to reset and
> interrupt on MR0, you will have an interrupt each time TC counts 10x10^6
> clocks, or, you will have an interrupt each second.
> On Mon, Aug 12, 2013 at 1:32 AM, Nick wrote:
>
> > **
> >
> >
> > Hey guys I could use some help. I have a LPC1764 running at 100MHz and I
> > am using LPC expresso 5.2.6. I am following the LPCX176x_cmsis2_timer
> > example provided.
> >
> > I see that the timer intervals are defined as follows:
> >
> > #define TIMER0_INTERVAL ((2 * (4 *(SystemCoreClock/10))) - 1)
> > #define TIMER1_INTERVAL ((2 *(4 *(SystemCoreClock/10))/3) - 1)
> > #define TIMER2_INTERVAL ((2 *(4 *(SystemCoreClock/10))/5) - 1)
> > #define TIMER3_INTERVAL ((2 *(4 *(SystemCoreClock/10))/7) - 1)
> >
> > Then I see in the init_timer function:
> >
> > LPC_TIM0->MR0 = TimerInterval;
> >
> > My question is why does the system core clock need to be multiplied by 2
> > and 4. How exactly are they calculating these values. For instance the
> > LPC1764 I have is 100MHz, so (2*4*100MHz/10)-1 => ~80x10^6 or ~80
million.
> > When I test it using the timer interrupt provided, it appears to be about
4
> > seconds.
> >
> > So, I'm not sure of the duration of each of these intervals and how
the
> > calculations work and how the MR0 (match register 0) function woks. If
> > anyone can help clear this up for me it would be much appreciated. Thank
> > you.
> >
> >
> > --
> Skype: felipeanl
> [Non-text portions of this message have been removed]
>