Reply by kunil November 3, 20062006-11-03
Well, I don't have any Spartan 3E starter kit or any experience with
Xilinx EDK, but I have some suggestions for you

1) Design with soft-core processors involves 2-things : hardware design
and software design.

When you download the bit stream, you're just configuring the FPGA (i.e
bring microblaze alive from LUTs). Your software hasn't run yet.

To run the software, enable microblaze JTAG (I think xilinx call it
debug hardware or something to avoid confusion with other JTAG to
upload the FPGA bitstream). Then, connect the JTAG (to upload the
software, not for the bitstream..I'm not sure they're interchangeable)
into microblaze's JTAG port. Then, using the GDB (am I right ? I think
EDK is based on GCC), open the JTAG in PC and upload the your firmware.

2) How to run in DDR ?
Use your software JTAG to upload the firmware directly in DDR. Don't
forget to set microblaze's boot memory into DDR address.

3) "Region XXX is full" error
It means you need to fix the linker script. Normal linker script
usually assumes that the firmware is booted from ROM. So any codes
should put in ROM. Since you won't use ROM as boot memory, you need to
fix the linker script to put all of the codes in DDR region.

4) Avoid downloading bitstream all the times
Buy a PROM chip, then burn the bitstream into that PROM. You'll save
yourself from the hassle of bitstream downloading..If you don't have
PROM programmer, I think the new Spartan-3E can use SPI EEPROM which
you can program from AVR or something.

Anyway, a bit out of topic, where can I buy Spartan-3E development kit
and its device (XC3S100E-4VQ100) in HK ? I want to have it too =)

-daniel
Denpasar - Bali - Indonesia

Reply by Steve November 2, 20062006-11-02
I'm writing a software for microblaze soft processor (Spartan 3E Starter 
Kit) and I have a few questions regarding the using of memory.

The first question is where my code is running? The starter kit has an 
external 64MB DDR memory and internal local memory (Use BRAM). When I 
download the bit stream to the FPGA, where is the program running? It seems 
it is running in the local memory.

Since the local memory is not big enough, for large size elf it should be 
running inside the DDR. I faced the error "region ilmb_cntlr_dlmb_cntlr is 
full" and I guess it's caused by the samll size local memory. Can anybody 
tell me how I can make my program run from the DDR? Do I need to develop a 
BSP for that?

Normally the tutorial tell us the "Mark to Initialize BRAMs", that why I 
guess the code is downloaded to the BRAM instead of the external DDR. What's 
the real meanning behind this step?

It seems the only method to update the code on FPGA is re-download the bit 
file. However, since the hardware has been fixed and we don't change the 
hardware much, is there a method that we can only update the software part 
without touching the whole bit file?

Thanks a lot.

JJ