On Tue, 28 Nov 2006 19:01:25 GMT, PeteS <peter.smith8380@ntlworld.com>
wrote:
>Tom Lucas wrote:
>> "RR" <richardrooney@icecomms.net> wrote in message
>> news:1164731384.051639.309660@l39g2000cwd.googlegroups.com...
>>> I need to interface a minimum of 32 (maximum of 64) 14-bit ADCs to an
>>> Intel PXA255 XScale processor.
>>> Each ADC is connected to an individual linear Hall Effect sensor.
>>> The sensors are distributed over an area of approx 2 sq metres. I want
>>> an ADC near each Sensor (for signal integrity reasons), so
>>> multi-channel ADCs are not suitable.
>>>
>>> The PXA255 has I2C and SSP ports available.
>>>
>>> Does anyone have any reccomendations on how I might best do this
>>> (taking into account signal integrity, loading, addressing issues,etc)
>>> ?
>>
>> Sounds to me like you might want to drive the ADCs from an FPGA and then
>> access the results with a memory-like interface to the processor.
>>
>>
>
>I am doing precisely this in a design. It gives a great deal of control
>over the access sequence and fixes up the broken behaviour of the PXA255
> SPI implementation (yes, it's broken). I make the FPGA a simple
>asynchronous memory target.
>
>Cheers
>
>PeteS
Hi Pete
I'm using SPI with the PXA255 - can you tell me what issues you have
found with it?
Cheers
Vic
Reply by PeteS●November 28, 20062006-11-28
Tom Lucas wrote:
> "RR" <richardrooney@icecomms.net> wrote in message
> news:1164731384.051639.309660@l39g2000cwd.googlegroups.com...
>> I need to interface a minimum of 32 (maximum of 64) 14-bit ADCs to an
>> Intel PXA255 XScale processor.
>> Each ADC is connected to an individual linear Hall Effect sensor.
>> The sensors are distributed over an area of approx 2 sq metres. I want
>> an ADC near each Sensor (for signal integrity reasons), so
>> multi-channel ADCs are not suitable.
>>
>> The PXA255 has I2C and SSP ports available.
>>
>> Does anyone have any reccomendations on how I might best do this
>> (taking into account signal integrity, loading, addressing issues,etc)
>> ?
>
> Sounds to me like you might want to drive the ADCs from an FPGA and then
> access the results with a memory-like interface to the processor.
>
>
I am doing precisely this in a design. It gives a great deal of control
over the access sequence and fixes up the broken behaviour of the PXA255
SPI implementation (yes, it's broken). I make the FPGA a simple
asynchronous memory target.
Cheers
PeteS
Reply by Jim Granville●November 28, 20062006-11-28
RR wrote:
> I need to interface a minimum of 32 (maximum of 64) 14-bit ADCs to an
> Intel PXA255 XScale processor.
> Each ADC is connected to an individual linear Hall Effect sensor.
> The sensors are distributed over an area of approx 2 sq metres. I want
> an ADC near each Sensor (for signal integrity reasons), so
> multi-channel ADCs are not suitable.
>
> The PXA255 has I2C and SSP ports available.
>
> Does anyone have any reccomendations on how I might best do this
> (taking into account signal integrity, loading, addressing issues,etc)
> ?
You'll need Serial ADCs - and some sort of a MUX scheme.
One ADC candidate would be TI's new ADS1230
- specs 5MHz SLCK
Ideal would be SPI ADCs that can be wired in a daisy-chain loop,
which would work very well with the SSP, but I don't recall seeing
an ADC that is quite that clever.
-jg
Reply by Tom Lucas●November 28, 20062006-11-28
"RR" <richardrooney@icecomms.net> wrote in message
news:1164731384.051639.309660@l39g2000cwd.googlegroups.com...
>I need to interface a minimum of 32 (maximum of 64) 14-bit ADCs to an
> Intel PXA255 XScale processor.
> Each ADC is connected to an individual linear Hall Effect sensor.
> The sensors are distributed over an area of approx 2 sq metres. I want
> an ADC near each Sensor (for signal integrity reasons), so
> multi-channel ADCs are not suitable.
>
> The PXA255 has I2C and SSP ports available.
>
> Does anyone have any reccomendations on how I might best do this
> (taking into account signal integrity, loading, addressing issues,etc)
> ?
Sounds to me like you might want to drive the ADCs from an FPGA and then
access the results with a memory-like interface to the processor.
Reply by RR●November 28, 20062006-11-28
I need to interface a minimum of 32 (maximum of 64) 14-bit ADCs to an
Intel PXA255 XScale processor.
Each ADC is connected to an individual linear Hall Effect sensor.
The sensors are distributed over an area of approx 2 sq metres. I want
an ADC near each Sensor (for signal integrity reasons), so
multi-channel ADCs are not suitable.
The PXA255 has I2C and SSP ports available.
Does anyone have any reccomendations on how I might best do this
(taking into account signal integrity, loading, addressing issues,etc)
?
RR