>Gordon Doughman <> wrote:
>>With the TFFCA bit set, the normal flag clearing mechanism does not
>>work.
>>
>
>Thanks for the confirmation, Gordon.
>
>Reading again "MC68HC912D60A Rev 3.0" I find that this behaviour
is
>not documented. Do you think it's useful I file a service request, or
>do you have better communication channels?
>
>Oliver
>
Reply by Oliver Betz●April 1, 20042004-04-01
Gordon Doughman <> wrote:
> With the TFFCA bit set, the normal flag clearing
mechanism does not
> work.
Thanks for the confirmation, Gordon.
Reading again "MC68HC912D60A Rev 3.0" I find that this behaviour is
not documented. Do you think it's useful I file a service request, or
do you have better communication channels?
Oliver
--
Oliver Betz, Muenchen
Reply by Gordon Doughman●March 31, 20042004-03-31
Oliver,
With the TFFCA bit set, the normal flag clearing mechanism does not work.
Regards,
Gordon
===============================================================
Gordon Doughman Ph: 937-438-6811
Motorola Semiconductor Fax: 937-434-7457
Field Applications Engineer Pager: 800-759-8352 Pin: 1304089
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Miamisburg, OH 45342
>Hello All,
>
>using a timer output compare interrupt, I tried to reset the
>corresponding bit in TFLG1 by writing a '1' to it.
>
>This didn't seem to work - only the "fast clear" mechanism
worked
>(writing TCx).
>
>Is this:
>
>- my error (wrong observation),
>- by design (and documentation error),
>- a D60A error?
>
>Would be nice if anybody could confirm this.
>
>Oliver
>
Reply by Oliver Betz●March 31, 20042004-03-31
Hello All,
using a timer output compare interrupt, I tried to reset the
corresponding bit in TFLG1 by writing a '1' to it.
This didn't seem to work - only the "fast clear" mechanism worked
(writing TCx).
Is this:
- my error (wrong observation),
- by design (and documentation error),
- a D60A error?