karthikbg wrote:
> Hi,
>
> I have some queries based on the MPU Clock/Reset/Power Mode Control
> Registers of OMAP 5912 and 5910.
>
> Does the term "OMAP 3.2 hardware engine" mentioned in OMAP 5912
> technical document refer to the term "DSP" mentioned in OMAP 5910
> technical document.
>
> Pls find the snapshot of the info  :
>
> In OMAP 5912
> =============
> ARM_RSTCT1  -  MPU Reset Control 1 Register  . This is a 32-bit
> register.
>
> Bit 3 - If set, Resets the OMAP 3.2 hardware engine. Once set to logic
> 1 by the MPU core processor, this bit returns to logic 0 on the next
> cycle.
>
> Bit 0 - If set, Resets the MPU core. Once set to 1 by the MPU core,
> this bit returns to 0 on the next cycle.
>
>
> In the case of OMAP 5910
> ======================
>
> ARM_RSTCT1 - Initiates the S/W reset to the MPU and DSP . THis is a
> 16-bit register.
>
> Bit 3 - If set,  Resets the DSP, MPU, and peripherals (the bit is
> always read 0):
>
> Bit 0 - If set, Resets the MPU . Once set to 1 by the MPU core, this
> bit returns to 0 on the next cycle.
>
>
> Thx in advans,
> Karthik Balaguru

Hi,

The below is extracted from the datasheets of OMAP 5910 and 5912  when
we set '1' or '0' in the ARM_RSTCT1 register (0xFFFFCE10).

OMAP 5910
============
0     The DSP, MPU, and peripheral clock domain is enabled
1     The DSP, MPU, and peripherals are reset-once set to logic 1 by
the MPU
       processor, this bit returns to logic  0 once the reset
completes.

OMAP 5912  :
===========
0:     The DSP, the MPU, and the peripheral clock domains are enabled.
1:     Resets the OMAP 3.2 hardware engine. Once set  to logic 1 by the
MPU
        processor, this bit returns to logic 0 on the next cycles.

As we find above, if we set '0' , the DSP, MPU and peripheral clock
domains are enabled for both 5910 and 5912.

But, if we set '1' , I think, they mean the same but TI have used a
different convention .
So, Does DSP + MPU + Peripherals together refer to the OMAP 3.2
hardware engine ?

Kindly clarify me . What does the hardware engine refer to here ?
Is it equivalent to DSP + MPU + Peripherals or Does to refer to some
other internal
engine in OMAP ?

What does the OMAP 3.2 hardware engine refer here ?

Thx in advans,
Karthik Balaguru

Hi,

I have some queries based on the MPU Clock/Reset/Power Mode Control
Registers of OMAP 5912 and 5910.

Does the term "OMAP 3.2 hardware engine" mentioned in OMAP 5912
technical document refer to the term "DSP" mentioned in OMAP 5910
technical document.

Pls find the snapshot of the info  :

In OMAP 5912
=============
ARM_RSTCT1  -  MPU Reset Control 1 Register  . This is a 32-bit
register.

Bit 3 - If set, Resets the OMAP 3.2 hardware engine. Once set to logic
1 by the MPU core processor, this bit returns to logic 0 on the next
cycle.

Bit 0 - If set, Resets the MPU core. Once set to 1 by the MPU core,
this bit returns to 0 on the next cycle.


In the case of OMAP 5910
======================

ARM_RSTCT1 - Initiates the S/W reset to the MPU and DSP . THis is a
16-bit register.

Bit 3 - If set,  Resets the DSP, MPU, and peripherals (the bit is
always read 0):

Bit 0 - If set, Resets the MPU . Once set to 1 by the MPU core, this
bit returns to 0 on the next cycle.


Thx in advans,
Karthik Balaguru