> --- In , "Bob Smith"
<bobsmith5@v...> wrote:
> > Although it seems, on first glance, that updating a circular (ring)
buffer
> > may need to be atomic, if you will look very
carefully at how the
>
> Excuse my ignorance Bob, but I seem to miss something, "atomic"
in my mind
is associated with interrupts that can occur in the middle of an
instruction
cycle, say a DMA event that occurs on a clock boundary thereby leaving the
current instruction partially completed.
>
> Does something like this occur in the Motorola devices?
>
> Regards,
>
> Theo
>
Theo --
Before addressing your question, we need to re-establish the context of this
thread. It is gotten a bit "over-snipped".
From the original posting on the topic by Sydney Faria
--
"I also just ran into a need for something like SCI using ints and was
thinking of doing something like setting up a routine to send one char via
SCI_isr and the receiver would be based on receiving a char and putting it
into a circular buffer. Accessing the circular buffer with a pointer and
storing into the buffer would have to be atomic so using tpa and tap to save
CCR would be necessary when adjusting the PUT and GET pointers is concerned.
Valvano's book (University of Texas site) covers this subject very
well."
At the risk of starting a contentious debate involving hair splitting over
the many meanings and uses of the word "atomic" I will describe my
thinking.
When I use "atomic" in this context, I am thinking of a
"indivisible
process". That 'process' can be:
1. As you describe, a single instruction which must not be interruptible.
2. A sequence of instructions which must not be interrupted.
3. A longer sequence of instructions such as an interrupt handler which
must not be interrupted.
In my experience the application of the term "atomic" has been very
loose
with regard to the above categories and I will not argue which one, if any
of them, is correct. I use and interpret the term interchangeably in all
three contexts.
To me the essential requirement is that you understand the concept of an
"indivisible process".
As a direct answer to your question, I assert that I have used the term
"atomic", in this context, in the same manner as the author of the
original
post.
That usage fits Category 2 of those stated above.
To further answer your question --
A Type 1 process (above) can only occur on so called Read-Modify-Write
instructions and then only on CPU's which permit some instructions to be
interrupted during execution before their processing is complete. To the
best of my knowledge, the low end Motorola MCUs such as the HC05_08 family,
the HC11, family, and _probably_ the HC12 family as well (since the HC12 is
stated to be source code upward compatible from the HC11), do not have _any_
interruptible instructions. In these MCU's, interrupts only occur
_between_
instructions (more accurately, during the instruction pre-fetch phase).
Once instruction fetch has begun (I-phase), any interrupts which are
recognized by the MCU hardware are held pending and are only recognized
during the pre-fetch phase of the _next_ instruction.
Thus, for this class MCU, it is important that the user recognize the RMW
class instructions as they can be used to fetch a semaphore, modify it, and
update it all in one indivisible sequence that does not have to protected by
disabling interrupts. The story is not so neat when one
grows beyond the low end class of Motorola MCUs however. When you get to
the larger MCUs such as the MC68332 (CPU32) family, for example, you begin
to encounter certain instructions that can, in fact, be interrupted during
execution and initiate exception processing. Those who are masochistic
enough to want to pursue this bizarre, and sometimes very complex, world
should refer to the M68300 CPU32 Reference Manual, CPU32RM/AD, Section 6,
"Exception Processing". Recovery from such "exceptions" and
restarting the
interrupted instruction can become a very challenging process.
With regard to Category 2, above, covering brief sequences of instructions
which must be implemented as an "atomic" (or indivisible) process,
consider
the management of the head and tail pointers in a circular buffer scheme.
Since there is, _generally_ _speaking_, no single instruction in the low end
MCU family that will retrieve a buffer pointer, increment it, test for end
of buffer, and, finally, save the updated pointer, the user must write a
'sequence' of (usually) 4-5 instructions to perform this process. If
it is
possible that this sequence could be interrupted by an event that would
would also try to manipulate the _same_ buffer pointer, then that sequence
must be protected by masking interrupts during its execution which makes it
an indivisible or "atomic" sequence.
Side note -- Actually, with the Motorola "low end MCU's" where
there is
always an INC (increment eight bit memory location) instruction this whole
mess can be
neatly sidestepped _if_ you have sufficient RAM resources. Make your ring
buffers 256 bytes long and the buffer pointers eight bit variables. Now
update the buffer pointer with a single INC instruction which will increment
the current pointer and if it wraps 256 bytes ($FF), it will overflow and
wrap back to $00. Viola!
Category 3, above is merely an extension of the above discussion since the
whole ISR normally runs disabled and is, therefore, by definition, an
indivisible or "atomic" process.
Best wishes, Bob Smith
--- Avoid computer viruses, Practice safe hex ---
-- Specializing in small, cost effective
embedded control systems --
http://www.smithmachineworks.com/embedprod.html
Robert L. (Bob) Smith
Smith Machine Works, Inc.
9900 Lumlay Road
Richmond, VA 23236 804/745-1065
----- Original Message -----
From: "theobee00" <>
To: <>
Sent: Saturday, April 17, 2004 2:05 PM
Subject: [68HC12] Re: Serial Communication
> --- In , "Bob Smith"
<bobsmith5@v...> wrote:
> > Although it seems, on first glance, that updating a circular (ring)
buffer
> > may need to be atomic, if you will look very
carefully at how the
>
> Excuse my ignorance Bob, but I seem to miss something, "atomic"
in my mind
is associated with interrupts that can occur in the middle of an
instruction
cycle, say a DMA event that occurs on a clock boundary thereby leaving the
current instruction partially completed.
>
> Does something like this occur in the Motorola devices?
>
> Regards,
>
> Theo
>
> --------------------To learn more
about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu
> o learn more about Motorola Microcontrollers, please visit
> http://www.motorola.com/mcu
>
>
> --
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