On 15 Apr 2005 at 0:09, Jane Highland wrote: > > > > How about DMA controller (say 4 channel) period.? > > > > But while we're on the subject of crappy or non existent > > peripherals... > > > > What we really want in terms of Serial ports, Sensible I/O > > configuartion, is something more like what Hitachi (Renesas) have > > always had (SH1, SH2 H8/300H etc). The peripherals are rich, > > extremely flexible, and always perform 100% as per data sheet - they > > are always logically thought out. You can start reading a section on > > a particular peripheral, and guess the rest, because the design is > > designed by engineers who care. The peripherals are beautiful. On > > most Renesas MCUs you can DMA from any peripheral to any other. > > I've worked on many (approx 20) H8/500 H8/300H, SH7032 SH7043 > > SH7709 projects and I can't remember a single erata sheet. The chips > > must have been tested to death, and were a dream to work with. My > > experience with Philips is a lot different, but I am told, 'well > > that's just Philips for you, If you want chips that work as per > > manual, and are well documented, stick with Hitachi...' > > > > But...the LPC2xxx is temping for new designs, because of lower cost, > > and of course they're based on ARM - you can always migrate to other > > ARMs without wasting too much of your investment in tools, time, > > and energy. > > > > The ideal chip: ARM core but with Renesas style peripherals. > > > > If Renesas ever launched a new family of MCU with ARM cores, eveyone > > other supplier would get a run for their money... > > > > Jane The Motorola / Freescale peripherals are also extremely well thought out. Very flexible, but clear and easy to get the basics going. So far only one of their ARM MCUs are available for general customers, but at least it is quite feature rich. Regards Anton Erasmus > > Robert Adsett wrote: > > > >> At 02:10 PM 4/14/05 -0500, Bill Knight wrote: > >> >One small feature I would like is to have an interrupt generated > >> >as the THRE interrupt is enabled, if the THRE bit is already set. > >> >This allows characters to be placed into an ouput queue and the > >> >THRE interrupt enabled as a means of both starting a transmission > >> >as well as adding characters to a transmission in progress. It > >> >also allows the forground process to do it without ever disabling > >> >global interrupts. > >> > >> While we're at it, how about a pseudo-DMA process to deal with the > >> I/O? That would reduce/eliminate the need for FIFO's. > >> > >> Robert > >> > >> " 'Freedom' has no meaning of itself. There are always > >> restrictions, be > >> they legal, genetic, or physical. If you don't believe me, try to > >> chew a radio signal. " -- Kelvin Throop, III > >> http://www.aeolusdevelopment.com/ > >> > > > > Yahoo! Groups Links > > -- A J Erasmus

An Engineer's Guide to the LPC2100 Series

> How about DMA controller (say 4 channel) period.? > > But while we're on the subject of crappy or non existent peripherals... > > What we really want in terms of Serial ports, Sensible I/O > configuartion, is something more like what Hitachi (Renesas) have > always had (SH1, SH2 H8/300H etc). The peripherals are rich, extremely > flexible, and always perform 100% as per data sheet - they are always > logically thought out. You can start reading a section on a particular > peripheral, and guess the rest, because the design is designed by > engineers who care. The peripherals are beautiful. On most Renesas > MCUs you can DMA from any peripheral to any other. I've worked on > many (approx 20) H8/500 H8/300H, SH7032 SH7043 SH7709 projects and I > can't remember a single erata sheet. The chips must have been tested > to death, and were a dream to work with. My experience with Philips is > a lot different, but I am told, 'well that's just Philips for you, If > you want chips that work as per manual, and are well documented, stick > with Hitachi...' > > But...the LPC2xxx is temping for new designs, because of lower cost, > and of course they're based on ARM - you can always migrate to other > ARMs without wasting too much of your investment in tools, time, and > energy. > > The ideal chip: ARM core but with Renesas style peripherals. > > If Renesas ever launched a new family of MCU with ARM cores, eveyone > other supplier would get a run for their money... > > Jane > > Robert Adsett wrote: > >> At 02:10 PM 4/14/05 -0500, Bill Knight wrote: >> >One small feature I would like is to have an interrupt generated as >> >the THRE interrupt is enabled, if the THRE bit is already set. This >> >allows characters to be placed into an ouput queue and the THRE >> >interrupt enabled as a means of both starting a transmission as well >> >as adding characters to a transmission in progress. It also allows >> >the forground process to do it without ever disabling global >> >interrupts. >> >> While we're at it, how about a pseudo-DMA process to deal with the >> I/O? That would reduce/eliminate the need for FIFO's. >> >> Robert >> >> " 'Freedom' has no meaning of itself. There are always >> restrictions, be >> they legal, genetic, or physical. If you don't believe me, try to >> chew a >> radio signal. " -- Kelvin Throop, III >> http://www.aeolusdevelopment.com/ >

At 02:10 PM 4/14/05 -0500, Bill Knight wrote: >One small feature I would like is to have an interrupt generated as >the THRE interrupt is enabled, if the THRE bit is already set. This >allows characters to be placed into an ouput queue and the THRE >interrupt enabled as a means of both starting a transmission as well >as adding characters to a transmission in progress. It also allows >the forground process to do it without ever disabling global >interrupts. While we're at it, how about a pseudo-DMA process to deal with the I/O? That would reduce/eliminate the need for FIFO's. Robert " 'Freedom' has no meaning of itself. There are always restrictions, be they legal, genetic, or physical. If you don't believe me, try to chew a radio signal. " -- Kelvin Throop, III http://www.aeolusdevelopment.com/

Yep, I just checked some old docs on the 16550 and sure enough, THRE is only set when the FIFO is empty - DUMB. And yep, it sure doesn't appear TEMT can be used to cause an interrupt - also DUMB. OK, I'm ready for a new, improved UART. One small feature I would like is to have an interrupt generated as the THRE interrupt is enabled, if the THRE bit is already set. This allows characters to be placed into an ouput queue and the THRE interrupt enabled as a means of both starting a transmission as well as adding characters to a transmission in progress. It also allows the forground process to do it without ever disabling global interrupts. -Bill On Thu, 14 Apr 2005 17:04:38 -0000, lp2000c wrote: Yes, you are missing something. THRE indicates when FIFO is empty - not when it is full. Furthermore, the exact time when this occurs, depends on "initialization conditions". See paragraph following Table 68 of LPC213x manual (or similar for other members of this family). As far as using TEMT for RS-485 turn-around, that would be great if it could be used to generate an interrupt. --- In lpc2000@lpc2..., "Bill Knight" <BillK@t...> wrote: > Am I missing something here guys (and gals)? When the FIFO is > enabled the THRE bit in the Line Status Register is set whenever > the FIFO can accept additional characters. So if it were clear, > isn't that an indication the FIFO is full? > As for RS-485 transceiver turn-around; the TEMT bit also in the > Line Status Register, can be used to determine when the stop bit > of the last character has been transmitted. Can't that be used > to control the RS-485 interface? > > Regards > -Bill Knight > R O SoftWare & > http://www.theARMPatch.com

--- In lpc2000@lpc2..., "Bill Knight" <BillK@t...> wrote: > Am I missing something here guys (and gals)? When the FIFO is > enabled the THRE bit in the Line Status Register is set whenever > the FIFO can accept additional characters. So if it were clear, > isn't that an indication the FIFO is full? Nope, that isn't the case. THRE is transmit holding register empty. There is the THRE register and then a 16 byte FIFO. So in my drivers, I just dump upto 16 bytes in the FIFO and then get an interrupt when they are all sent. I guess I could do 17, I'd have to try that. But there is no way to tell if it is full, unless you count how many you put in and keep track of the time and baud rate and all the error that can occur. But I find that dumping up to 16 chars in the fifo and they the next 16 when I get THRE. Its a little more overhead than just checking to see if the FIFO is full, but since you can't do that, this works well enough. > As for RS-485 transceiver turn-around; the TEMT bit also in the > Line Status Register, can be used to determine when the stop bit > of the last character has been transmitted. Can't that be used > to control the RS-485 interface? > > Regards > -Bill Knight > R O SoftWare & > http://www.theARMPatch.com

Yes, you are missing something. THRE indicates when FIFO is empty - not when it is full. Furthermore, the exact time when this occurs, depends on "initialization conditions". See paragraph following Table 68 of LPC213x manual (or similar for other members of this family). As far as using TEMT for RS-485 turn-around, that would be great if it could be used to generate an interrupt. --- In lpc2000@lpc2..., "Bill Knight" <BillK@t...> wrote: > Am I missing something here guys (and gals)? When the FIFO is > enabled the THRE bit in the Line Status Register is set whenever > the FIFO can accept additional characters. So if it were clear, > isn't that an indication the FIFO is full? > As for RS-485 transceiver turn-around; the TEMT bit also in the > Line Status Register, can be used to determine when the stop bit > of the last character has been transmitted. Can't that be used > to control the RS-485 interface? > > Regards > -Bill Knight > R O SoftWare & > http://www.theARMPatch.com

At 03:39 PM 4/14/05 +0000, johnthomasedwardtimm wrote: >I second that motion. I am using the THRE bit in the LSR to >determine >whether the transmit FIFO is full and it works fine. Have you actually checked how may bytes you get into the FIFO in that fashion ? Robert " 'Freedom' has no meaning of itself. There are always restrictions, be they legal, genetic, or physical. If you don't believe me, try to chew a radio signal. " -- Kelvin Throop, III http://www.aeolusdevelopment.com/

At 09:41 AM 4/14/05 -0500, Bill Knight wrote: >Am I missing something here guys (and gals)? When the FIFO is >enabled the THRE bit in the Line Status Register is set whenever >the FIFO can accept additional characters. So if it were clear, >isn't that an indication the FIFO is full? No, the THRE bit is cleared when something is ready to transmit, it is only set when the FIFO is empty. The only way to fill the FIFO is to count how many bytes you put in. I don't find that a big problem but it would be more efficient to be able to tell when the FIFO was full. I'll leave the End of transmission question to others who have had to deal with it. That still leaves the 9 bit mode problems. Robert " 'Freedom' has no meaning of itself. There are always restrictions, be they legal, genetic, or physical. If you don't believe me, try to chew a radio signal. " -- Kelvin Throop, III http://www.aeolusdevelopment.com/

> Second is that there is no way to tell if the transmit FIFO is full. Heh... you need to ASSUME, that when THRE gets generated, that you can stuff up to 16-bytes into that FIFO. Actually, my experience has shown that this is a pretty good assumption. Unfortunately, if you work under non-interrupt mode, this means you need to wait for the queue to completely drain before you can feel 'safe' in stuffing more bytes into the queue.... not the most efficient means to go in non-interrupt mode. Ken Wada

Indeed! You need...actually it is a very good idea to use the TEMT bit to toggle the transmit enable bit on your RS-485 interface. For me, it would have been nice to have the TEMT bit generate an interrupt. My code would have been a little bit more efficient in this way. As it stands, I now look for a signal that the interrupt service routine has processed the last byte out, (THRE interrupt, and no more bytes in tx queue). After this, I poll the TEMT bit. This lets me know that I will not 'clobber' that last byte out before disabling the transmitter on my RS-485 transceiver. Ken Wada --- In lpc2000@lpc2..., "Bill Knight" <BillK@t...> wrote: > Am I missing something here guys (and gals)? When the FIFO is > enabled the THRE bit in the Line Status Register is set whenever > the FIFO can accept additional characters. So if it were clear, > isn't that an indication the FIFO is full? > As for RS-485 transceiver turn-around; the TEMT bit also in the > Line Status Register, can be used to determine when the stop bit > of the last character has been transmitted. Can't that be used > to control the RS-485 interface? > > Regards > -Bill Knight > R O SoftWare & > http://www.theARMPatch.com