Reply by Ulf Samuelsson May 11, 20072007-05-11
"Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet 
news:46440fcd$1@clear.net.nz...
> Ulf Samuelsson wrote: >> The AVR32 SPI implementation does not synchronize the >> input clock with the internal clock. >> Instead the input clock will clock the flip flops >> in the SPI shift register and synchronization is >> done when the complete byte is read/written to holding register. >> Looking at the AT91 SPI block diagram shows that this is the same. >> No synchronization of the SPI clock in slave mode. >> >> I guess that any SAM7S should do as well then. > > So, then where-from the SYSCLK/2 limit ?. > What you describe should be able to clock faster on the slave ? > > -jg >
I do not know how the synchronization for the holding register works... -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Reply by Jim Granville May 11, 20072007-05-11
Ulf Samuelsson wrote:
> The AVR32 SPI implementation does not synchronize the > input clock with the internal clock. > Instead the input clock will clock the flip flops > in the SPI shift register and synchronization is > done when the complete byte is read/written to holding register. > Looking at the AT91 SPI block diagram shows that this is the same. > No synchronization of the SPI clock in slave mode. > > I guess that any SAM7S should do as well then.
So, then where-from the SYSCLK/2 limit ?. What you describe should be able to clock faster on the slave ? -jg
Reply by Ulf Samuelsson May 11, 20072007-05-11
>> >> Any schedule for the AT32UC3B family yet ? >> >> I'd imagine Antti's BOM target is not single Qty, as worrying about that >> detail of price only matters for > 10K levels. > > Jim, > your guess is very correct. > BOM cost difference of 0.80 USD matter at qty >10K >
The AVR32 SPI implementation does not synchronize the input clock with the internal clock. Instead the input clock will clock the flip flops in the SPI shift register and synchronization is done when the complete byte is read/written to holding register. Looking at the AT91 SPI block diagram shows that this is the same. No synchronization of the SPI clock in slave mode. I guess that any SAM7S should do as well then.
> Antti, > who also looks forward to see more AVR32 flash chips > >
Many are!!! -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Reply by Antti May 10, 20072007-05-10
On 10 Mai, 00:29, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Ulf Samuelsson wrote: > > "Jim Granville" <no.s...@designtools.maps.co.nz> skrev i meddelandet > >news:463eeb29$1@clear.net.nz... > > >>Antti wrote: > > >>>I guess none available :( > > >>>all seem limit to clock/4 or something > > >>>but maybe I have missed some good part? > > >>>The AT32UC3A0512 looks fast in master, but I did not > > >>see a fMAX in slave mode. > >>AT91SAM9260 info suggests ~32ns in slave, but lacks any > >>CLK ratio specs, and there must be some. > > > My firends at Atmel Nantes says that the SPI slave will work up to > > CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512. > > While this wont meet the $3, the AT32UC3B family should maybe be > > in the right price range, probably not in single qty though. > > Thanks Ulf. Is this true of all Atmel 32 bit SPI peripherals ? > (SAM7 and SAM9 ? ). > Where I have seen a 2x ceiling before, it > is sometimes qualified with Tsu,Th,Jitter, and duty cycle margins, > to be appx 2.5x as a 'practical ceiling'. It may be that some of > the 4x SPI specs are just rounding that again. > > Any schedule for the AT32UC3B family yet ? > > I'd imagine Antti's BOM target is not single Qty, as worrying about that > detail of price only matters for > 10K levels. > > -jg- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -
Jim, your guess is very correct. BOM cost difference of 0.80 USD matter at qty >10K Antti, who also looks forward to see more AVR32 flash chips
Reply by Jim Granville May 9, 20072007-05-09
Ulf Samuelsson wrote:

> "Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet > news:463eeb29$1@clear.net.nz... > >>Antti wrote: >> >>>I guess none available :( >>> >>>all seem limit to clock/4 or something >>> >>>but maybe I have missed some good part? >>> > > >>>The AT32UC3A0512 looks fast in master, but I did not >> >>see a fMAX in slave mode. >>AT91SAM9260 info suggests ~32ns in slave, but lacks any >>CLK ratio specs, and there must be some. >> > > > > My firends at Atmel Nantes says that the SPI slave will work up to > CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512. > While this wont meet the $3, the AT32UC3B family should maybe be > in the right price range, probably not in single qty though.
Thanks Ulf. Is this true of all Atmel 32 bit SPI peripherals ? (SAM7 and SAM9 ? ). Where I have seen a 2x ceiling before, it is sometimes qualified with Tsu,Th,Jitter, and duty cycle margins, to be appx 2.5x as a 'practical ceiling'. It may be that some of the 4x SPI specs are just rounding that again. Any schedule for the AT32UC3B family yet ? I'd imagine Antti's BOM target is not single Qty, as worrying about that detail of price only matters for > 10K levels. -jg
Reply by Ulf Samuelsson May 9, 20072007-05-09
"Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet
news:463eeb29$1@clear.net.nz...
> Antti wrote: >> I guess none available :( >> >> all seem limit to clock/4 or something >> >> but maybe I have missed some good part? >>
>> The AT32UC3A0512 looks fast in master, but I did not > see a fMAX in slave mode. > AT91SAM9260 info suggests ~32ns in slave, but lacks any > CLK ratio specs, and there must be some. >
My firends at Atmel Nantes says that the SPI slave will work up to CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512. While this wont meet the $3, the AT32UC3B family should maybe be in the right price range, probably not in single qty though. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Reply by Jim Granville May 7, 20072007-05-07
Ulf Samuelsson wrote:

> Subject: Flash mcu with SPI slave capable of 16MHz operation? > > > >>I guess none available :( >> >>all seem limit to clock/4 or something >> >>but maybe I have missed some good part? >> >>Antti >> > > Why need a flash MCU? Protection? > An AT91SAM9261 has 160 kB of internal SRAM which > can be used for code & data. > It can load the SRAM from a cheap 1 Mbit serial flash. > > Running the bus at 96 MHz you have 96/16 = 6 times > overclocking which should be good enough! > > Your CPU will run at 200 MIPS+ as well from the TCM.
Hi Ulf, Antti since came back with another detail - a $3US budget ;) - but while you are here, what is the MAX Slave clock speed for the AT32UC3A0512 ? Antti: I did find the infineon XC2200 specs this [SSC/SPI/QSPI (synchronous serial channel with or without data buffer) &#4294967295; maximum baud rate in slave mode: fSYS &#4294967295; maximum baud rate in master mode: fSYS / 2 &#4294967295; number of data bits programmable from 1 to 63, more with explicit stop condition &#4294967295; MSB or LSB first &#4294967295; optional control of slave select signals] Not sure if that is a typo, as they claim faster Slave than Master ?, - out of step with everyone else. Nice part/peripheral, but the XC2200 family are starting at the top, and releasing downwards (as is the AT32UC3A0512 ), so neither are going to hit $3 until smaller ones come along... -jg
Reply by Ulf Samuelsson May 7, 20072007-05-07
Subject: Flash mcu with SPI slave capable of 16MHz operation?


>I guess none available :( > > all seem limit to clock/4 or something > > but maybe I have missed some good part? > > Antti >
Why need a flash MCU? Protection? An AT91SAM9261 has 160 kB of internal SRAM which can be used for code & data. It can load the SRAM from a cheap 1 Mbit serial flash. Running the bus at 96 MHz you have 96/16 = 6 times overclocking which should be good enough! Your CPU will run at 200 MIPS+ as well from the TCM. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Reply by Jim Granville May 7, 20072007-05-07
Antti wrote:

> Hi Jim, > > you made summary of what I was afraid the situation is. > BOM cost needs to be around 3USD and it must be available now. > > I possible have to go CPLD+MCU (BOM 2.8USD) or even FPGA+MCU (BOM > 3.90USD) > there is also PCB space constraints so only can use microBGA or small > QFN > if I can fit the needed stuff into XC9572XL then I may use that > solution. > the function needed is rather simple, so I was hoping to reduce the > component > count to flash mcu only. optionally could use 1 FPGA but that would > kill BOM limits. > > the gadget is special serial memory emulator, > that need to handle certain protocol at 16mhz. > it doesnt directly map to any available spi flash memories, so need > kind of serial protocol converter.
How much code Size / CPU muscle appx do you need ? -jg
Reply by Antti May 7, 20072007-05-07
On 7 Mai, 11:03, Jim Granville <no.s...@designtools.maps.co.nz> wrote:
> Antti wrote: > > I guess none available :( > > > all seem limit to clock/4 or something > > > but maybe I have missed some good part? > > > Antti > > Hi Antti, > No, I think you are pretty much right. > There are ones that will run typically /2 on master mode, > but to operate in slave, takes more clocks (/4 or more), and some are > many more(/10). > > So, generaly you'd need to target the fastest clock speeds, to > get 16MHz, > 64MHz, or 128MHz is suggested. > > The AT32UC3A0512 looks fast in master, but I did not > see a fMAX in slave mode. > AT91SAM9260 info suggests ~32ns in slave, but lacks any > CLK ratio specs, and there must be some. > > AT91SAM9XE512 is the upcomming flash ARM9, which is likely > to have a high CPU Clk, so give better peripheral speeds. > > The C8051F41x slave is /10 full duplex, and /4 half duplex, makes > 5Mhz and 12.5Mhz slave speeds. > > AT89LPxx spec /4 in fastest SPI mode. > > LPC24xx specs CLK/8 as fmax. > > I think they all sample the SPI pins, as being simplest. > Easiest to design and test. > In theory, I guess one could dual port a SPI, and have a genuine > high slave speed, but that's not an area the designers have targeted. > > You could always use a CPLD, if it must run in slave mode ? > > -jg
Hi Jim, you made summary of what I was afraid the situation is. BOM cost needs to be around 3USD and it must be available now. I possible have to go CPLD+MCU (BOM 2.8USD) or even FPGA+MCU (BOM 3.90USD) there is also PCB space constraints so only can use microBGA or small QFN if I can fit the needed stuff into XC9572XL then I may use that solution. the function needed is rather simple, so I was hoping to reduce the component count to flash mcu only. optionally could use 1 FPGA but that would kill BOM limits. the gadget is special serial memory emulator, that need to handle certain protocol at 16mhz. it doesnt directly map to any available spi flash memories, so need kind of serial protocol converter. Antti