Reply by Hugh Molesworth●October 9, 20022002-10-09
I'd look for a pattern of those 10 bad samples in 4000. If it
isn't
obvious, put a port pin pulse within the ADC interrupt and use that to
trigger a scope and capture the analog input at that instant and any other
external signal interrupts (easier with a digital scope so you can scroll
back in time). If nothing tallies look at the Vcc rail or any changing
outputs using the same trigger.
Something "physical" might be happening to cause your bad samples.
One last thought, make sure you're not changing ADC register values with
the ADC interrupt running and capturing data.
--- In msp430@y..., Hugh Molesworth <nzbackpackers@y...> wrote:
> 100u is way too high but I guess it will do; a few
nF should
suffice but
> use something better than an MLC.
>
> Are you averaging the 4000 samples? If so the problem is worse than
it
> looks so I hope your jitter is between individual
samples.
Thanks for your comments first.
No, I didn't do any averaging. Among the 4000 samples, the different
between the maximum value and minimum value is 90 before adding the
cap and 24 after adding the cap.
Notice that the critical samples (those maximum and minimum values)
just appear sometimes. (e.g. 10 samples among the 4000).
>
> I would suggest you open out the sample-hold time and see what
happens (see
> previous email). I think that is the starting
point - set the
maximum value.
>
> Are you pulsing LEDs or anything like that while taking the series
of readings?
>
> You might email your ADC12CTL0 and ADC12CTL1 settings (I mean from
the
> output assembler files); maybe there is something
not quite right.
Some of
> the old C include files do not correctly enclose
#defines within
braces and
> this can sometimes lead to setting a register to
an incorrect value
> depending on how you combine fields from those files. If that
happened to
> your reference, for instance, and you were using
Vcc/2 instead of
the fixed
> reference then any power activity which affected
Vcc would alias
into
> instability into a series of ADC readings against
an input not also
> affected by Vcc in a ratiometric manner (again, see previous
email). For
> best performance, if you want common mode power
supply rejection
for
> signals affected by Vcc use Vcc/2; for signals
independent of Vcc
use the
> fixed reference.
>
> Good luck.
Reply by Hugh Molesworth●October 9, 20022002-10-09
100u is way too high but I guess it will do; a few nF should suffice but
use something better than an MLC.
Are you averaging the 4000 samples? If so the problem is worse than it
looks so I hope your jitter is between individual samples.
I would suggest you open out the sample-hold time and see what happens (see
previous email). I think that is the starting point - set the maximum value.
Are you pulsing LEDs or anything like that while taking the series of readings?
You might email your ADC12CTL0 and ADC12CTL1 settings (I mean from the
output assembler files); maybe there is something not quite right. Some of
the old C include files do not correctly enclose #defines within braces and
this can sometimes lead to setting a register to an incorrect value
depending on how you combine fields from those files. If that happened to
your reference, for instance, and you were using Vcc/2 instead of the fixed
reference then any power activity which affected Vcc would alias into
instability into a series of ADC readings against an input not also
affected by Vcc in a ratiometric manner (again, see previous email). For
best performance, if you want common mode power supply rejection for
signals affected by Vcc use Vcc/2; for signals independent of Vcc use the
fixed reference.
Good luck.
Reply by chowkamfai●October 9, 20022002-10-09
Thanks for you comments first, Hugh. Here is some further notes and
observations:
--- In msp430@y..., Hugh Molesworth <nzbackpackers@y...> wrote:
> Four points you might consider:
>
> 1. You don't mention what you're doing with adjacent
channels.>
I just capture one channel. Other channels are not used.
> 2. The input circuitry to the ADC additionally
consumes a dollop of
charge
> at the sampling instant; if you have a high input
impedance you
will need
> to add a capacitor bucket to stop this transfer of
charge affecting
the
> input voltage at the time of sampling. You can see
if this is the
case by
> temporarily adding a capacitor across your input
and analog ground.
Again
> you can help control this by increasing the a/d
sampling interval
> (Sample/Hold time) SHT0 in register ADC12CTL0 to suit
I measured a 1.4V battery using 2.5V internal ref. Without a input
capacitor (original config), the digital value captured has a range
of 90 (around +- 5 to 6 bits) out of 4096.
After I added a capacitor (100u) at the ADC input, the range of value
becomes 24 (around +- 3 to 4 bits) out of 4096.
What 's the imprication? The charge comsumption of the ADC input is
too large?
Notice that I take around 4000 samples with period around 2 ms.
Please comments.
Reply by Hugh Molesworth●October 8, 20022002-10-08
Four points you might consider:
1. You don't mention what you're doing with adjacent channels. If
you're
scanning multiple channels remember to leave a sufficient settle time to
allow the input to charge to a stable level. For example, if the previous
channel you sample is at 0V and you're channel of interest is at (say) 1
volt with an effective charging time constant of CR you have to allow 5 x
CR (5 time constants) to charge to within a reading that's stable to within
1 bit (1/4096 of 1 volt) to allow a 12-bit measurement of the final
voltage, otherwise you will measure a value that's dependant on that
previous channel. You can do this by either controlling the input CR time
constant or by setting the a/d sampling interval (Sample/Hold time) SHT0 in
register ADC12CTL0 to suit. It's a good idea to set that to a maximum
anyway, look at stability and then gradually reduce it to see if the sample
time is affecting the reading.
2. The input circuitry to the ADC additionally consumes a dollop of charge
at the sampling instant; if you have a high input impedance you will need
to add a capacitor bucket to stop this transfer of charge affecting the
input voltage at the time of sampling. You can see if this is the case by
temporarily adding a capacitor across your input and analog ground. Again
you can help control this by increasing the a/d sampling interval
(Sample/Hold time) SHT0 in register ADC12CTL0 to suit
3. You might be seeing asynchronous AC pickup at 50/100Hz or 60/120Hz
(unlikely if you're on batteries). You can scale your triple variables
(sampling interval/number of channels sampled/ADC clock frequency) to be a
multiple of the AC line frequency so that you either sample an integral
number of AC line cycles (slower readings) or you sample at the same time
on each line cycle (faster readings). It helps to use a crystal reference
for this, and it can be a pain getting the sums right if you use an awkward
crystal frequency.
4. If the first 3 don't help, you might try going ratiometric. Set the
input voltage as a %-age of Vcc (which you may be doing already if your
battery supplies Vcc) by a resistor divider and use a Vcc/2 internal
reference. If this gives an immediate improvement then you are seeing Vcc
noise on your earlier circuit.
Hope this helps. We get +- 1 bit of jitter on a 430F149 12-bit ADC
(although we still use signal averaging to make it look really good).
Hugh
Reply by chowkamfai●October 8, 20022002-10-08
Hi,
I 'm using MSP430F449 which has a build-in 12 bits ADC. I use the
internal ref voltage (2.5V) as V+ and AVSS as V-. I measured a 1.4V
DC from a battery and found that there are some random noise of
around 30 mV, that is, with around 5-bits error.... which is not
acceptable. What I 've already done are:
- Seperate the AVCC and DVCC; AVSS and DVSS. They are jointed at the
power supply pin.
- Added 10u+0.1u bypass cap between AVCC and AVSS; DVCC and DVSS.
- Added 10u+0.1u between Vref+ and AVSS.
Did anyone use the build-in 12-bit ADC before? Can you share your
experience and the accuracy?
Thanks!!