On Sep 16, 9:37 am, "fpga_beginner" <cvol2...@yahoo.com> wrote:
> Hi all
> I have designed some FPGA based applications but very simple ones. Now I
> want to find some methods/algorithms in FPGA design to optimize power. I
> search many documents (IEEE,..) but they are not in detail. I need some
> free documents and open source (or only detail steps) to implement power
> optimize algorthm.

FPGAs are used in embedded systems, so
your questions are certainly appropriate for this
newsgroup.  But you are likely to get better
answers to FPGA specific questions by posting
to comp.arch.fpga.  That group is frequented by
FPGA geeks and tech reps from the various
FPGA vendors, and they often provide very
knowledgeable information.

> So i hope somebody can help me with useful links!

Techniques to reduce power are very dependent
on the specific part you are using.  You should
go to the vendors website, look up the part you
are using, and look for whitepapers and tech
reports on how to minimize power consumption.
For instance, you can go to www.xilinx.com and
type "low power" into the search box, and get
oodles of links.

Here is some general advice:

1.  Use a part that is designed for low power.
     Such as Coolrunner, or Spartan-3L series.
     Altera, Lattice, etc. also have parts designed
     to minimize power.

2.  Use the part with the lowest gate count
    that your application will fit into.  This will
    minimize power, but it will also take away
    some flexibility to add features or fix bugs.

3.  Run your application with the lowest clock
    freq that you can.

4.  Try to trim down and simplify your application.
     For instance, most FPGA designs include a
     global reset, but this is rarely necessary.

5.  If you really know what you are doing, you
     might be able to save some power by gating
     you clocks.  But this is considered a very
     bad design technique.

6.  Are you really sure you need an FPGA?
     If a microcontroller, such as an ARM or
     AVR is fast enough to run you application,
     it will probably use considerably less
     power than an FPGA.

On Sep 16, 10:57 am, Tim Wescott <t...@seemywebsite.com> wrote:
> On Sun, 16 Sep 2007 11:37:01 -0500, fpga_beginner wrote:
> > Hi all
> > I have designed some FPGA based applications but very simple ones. Now I
>
> > want to find some methods/algorithms in FPGA design to optimize power. I
>
> > search many documents (IEEE,..) but they are not in detail. I need some
>
> > free documents and open source (or only detail steps) to implement power
>
> > optimize algorthm.
> > So i hope somebody can help me with useful links!
>
> > Thanks
>
> Are you looking to optimize the firmware for a given FPGA to minimize
> power, or are you looking to design an FPGA chip with power optimizations?
> You'd only be doing the latter if you were a student specializing in IC
> design, so I'll assume the more likely former case.
>
> This sort of thing is highly dependent on the particular chip you're
> working with.  The first place you should look is on the web sites for
> your FPGA vendor -- if power is the most critical parameter in your design,
> I'd start by choosing the FPGA that seems to be the best supported by it's
> vendor.
>
> In general you want to keep the clock speeds as low as you can, and to
> "flip" the fewest gates possible every second.  Having an FPGA that's
> optimized for power consumption will help; FPGA architectures tend to
> tickle more gates than you think, so you'd need one that's specifically
> made not to.  Until a decade ago no one cared at all whether their
> FPGA's consumed lots of power as long as they were fast and flexible; even
> today many FPGA users put power consumption low on their list when they're
> selecting chips.

Just one more thing.  Some FPGA are grouped in blocks for power, so
you can select your logic to minimize active power use.  Just a little
more planning in laying out your pins, rather than letting the
software to do it all.

>
> Good luck.  It sounds fun.
>
> --
> Tim Wescott
> Control systems and communications consultinghttp://www.wescottdesign.com
>
> Need to learn how to apply control theory in your embedded system?
> "Applied Control Theory for Embedded Systems" by Tim Wescott
> Elsevier/Newnes,http://www.wescottdesign.com/actfes/actfes.html

On Sun, 16 Sep 2007 11:37:01 -0500, fpga_beginner wrote:

> Hi all
> I have designed some FPGA based applications but very simple ones. Now I
> 
> want to find some methods/algorithms in FPGA design to optimize power. I
> 
> search many documents (IEEE,..) but they are not in detail. I need some
> 
> free documents and open source (or only detail steps) to implement power
> 
> optimize algorthm.
> So i hope somebody can help me with useful links!
> 
> Thanks

Are you looking to optimize the firmware for a given FPGA to minimize
power, or are you looking to design an FPGA chip with power optimizations?
You'd only be doing the latter if you were a student specializing in IC
design, so I'll assume the more likely former case.

This sort of thing is highly dependent on the particular chip you're
working with.  The first place you should look is on the web sites for
your FPGA vendor -- if power is the most critical parameter in your design,
I'd start by choosing the FPGA that seems to be the best supported by it's
vendor.

In general you want to keep the clock speeds as low as you can, and to
"flip" the fewest gates possible every second.  Having an FPGA that's
optimized for power consumption will help; FPGA architectures tend to
tickle more gates than you think, so you'd need one that's specifically
made not to.  Until a decade ago no one cared at all whether their
FPGA's consumed lots of power as long as they were fast and flexible; even
today many FPGA users put power consumption low on their list when they're
selecting chips.

Good luck.  It sounds fun.

-- 
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

Hi all
I have designed some FPGA based applications but very simple ones. Now I
want to find some methods/algorithms in FPGA design to optimize power. I
search many documents (IEEE,..) but they are not in detail. I need some
free documents and open source (or only detail steps) to implement power
optimize algorthm.
So i hope somebody can help me with useful links!

Thanks