On Oct 5, 12:36 am, Chandra <forquer...@gmail.com> wrote:

> required. Both the clock pulse and the data pulse should start at the
> same time.

Not really. If you're getting unexpected results then you probably
have a mismatch between the edge/sampling configuration on the two
ends.

The "real" order of "pulses" for a single bit is:
- clock goes to inactive state (say 0)
- master sets up data on MOSI, slave sets up data on MISO
- clock active (say 1)
- slave samples data on MOSI, master samples dara on MISO

Hi Guys,

I am working on ARM based processor (IMX31). I am having problem with
the SPI interface which i am using to interface with the other
devices. Here my problem is when i make a write operation to the SPI,
the data pulse is getting started before the clock pulse which is not
required. Both the clock pulse and the data pulse should start at the
same time. Hope you guys understand my problem. If i am not clear in
my words do tell me.


with regards,

Chandra.