On Oct 11, 9:56 pm, "Vagant" <vladimir.v.koroste...@rambler.ru> wrote:
> Hello,
>
> I want to design an FPGA-based system which is controlled by PC host
> through USB-parallel interface (I use UM245R module from FTDI). My system
> has several subsystems which have to have bidirectional data flow with
> host.
> There are two things which are not clear for me and I would be glad to get
> an advice on these.
> First, I do not understand how to organise communication through parallel
> output of the module. It has only 8 data lines, and for my system I wish
> to have 16-bit data and several additional lines for address bus.
> I wouldn't mind using the same bus as address bus and data bus but have no
> idea how to organise such bus.
> Second, what the interface between USB-parallel and FPGA has to be? -
> whether it is separate PCB of some controller or it can be programmed on
> FPGA using VHDL? What is most natural way to do such things?

I took a quick look at the UM245R docs.  It seems easy to use, not
much different than using a UART (serial) chip.  To write a byte to
the chip, first check the TXE# status pin.  You are only allowed to
write a byte to the chip when this pin is LO.  Your FPGA must put your
byte onto the 8-bit bus and then drive the WR pin HI.  See the doc's
timing figures for more info.  Note that you have to check TXE# prior
to _every_ write.  If you need to write 16-bits, then you will have to
break that into 2 8-bit values.  To read from the chip, first look at
the RXF# pin. when that is LO, then you can read a byte from the chip,
using the RD# pin.
HTH
-Dave Pollum

On Oct 11, 7:56 pm, "Vagant" <vladimir.v.koroste...@rambler.ru> wrote:
> Hello,
>
> I want to design an FPGA-based system which is controlled by PC host
> through USB-parallel interface (I use UM245R module from FTDI). My system
> has several subsystems which have to have bidirectional data flow with
> host.
> There are two things which are not clear for me and I would be glad to get
> an advice on these.
> First, I do not understand how to organise communication through parallel
> output of the module. It has only 8 data lines,

One can also argue that USB has only 1 data line, how can the FTDI
chip deal with 8 data lines.

> and for my system I wish
> to have 16-bit data and several additional lines for address bus.

It's just one more level of abstractions.

> I wouldn't mind using the same bus as address bus and data bus but have no
> idea how to organise such bus.
> Second, what the interface between USB-parallel and FPGA has to be? -
> whether it is separate PCB of some controller or it can be programmed on
> FPGA using VHDL? What is most natural way to do such things?

Use 1 data bit and 1 clock bit in FPGA to do USB.

Hello,

I want to design an FPGA-based system which is controlled by PC host
through USB-parallel interface (I use UM245R module from FTDI). My system
has several subsystems which have to have bidirectional data flow with
host.
There are two things which are not clear for me and I would be glad to get
an advice on these.
First, I do not understand how to organise communication through parallel
output of the module. It has only 8 data lines, and for my system I wish
to have 16-bit data and several additional lines for address bus.
I wouldn't mind using the same bus as address bus and data bus but have no
idea how to organise such bus.
Second, what the interface between USB-parallel and FPGA has to be? -
whether it is separate PCB of some controller or it can be programmed on
FPGA using VHDL? What is most natural way to do such things?