"CBFalconer" <cbfalconer@yahoo.com> wrote in message
news:473E3588.A515BB61@yahoo.com...
> Vladimir Vassilevsky wrote:

> > The last dynamic CPU probably was the original i8080. Since then all
> > general purpose CPU designs were static.
>
> IIRC the 8080 (and z80) was static. It could be halted without
> harm.

You couldn't stop a CPU clock, at least for the original i8080. However
there used to be many remakes of i8080 which were full static. Some even
could run on the single +5V supply,  whereas the original 8080 required +/-5
and +12. AFAIK the original Z80 was static, however there was a limit for
the maximum duration of the clock in low. Power dissipation?

BTW my favourite ~25 year old RPN calculator is P-MOS dynamic 4-phase serial
architecture.

Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com

Paul Keinanen wrote:
> CBFalconer <cbfalconer@yahoo.com> wrote:
>> Vladimir Vassilevsky wrote:
>>> larwe wrote:
>>>
>>>> In a dynamic processor (ie. one that cannot live if its clock
>>>> is stopped), the registers are essentially DRAM cells.
>>>
>>> There were two typical architectures for that purpose: two phase
>>> and four phase.
>>>
>>> The last dynamic CPU probably was the original i8080. Since then
>>> all general purpose CPU designs were static.
>>
>> IIRC the 8080 (and z80) was static. It could be halted without
>> harm.
> 
> The Z80 and possibly 8085 could have been static, but at least the
> TI variant of 8080 (TMS8080) specified 2 us maximum clock cycle
> time. Also the 8080 clock driver (8224) had high CPU clock drive
> capability (typically required by a dynamic construction). Also
> MC6800 needed quite high two phase clock drive capability and the
> clock frequency range was specified as 0.1-1 MHz, also suggesting
> a dynamic construction.
> 
> One of the sales arguments for the CMOS RCA 1802 was that it was
> fully static and the clock could be stopped or manually single
> stepped. This would suggest that many competitors did not have
> this capability at that time-

It is not impossible that my memory is faulty.  I know I could halt
my systems at any point at any time.  However, it might have been
continuous application of the wait signal.

-- 
 Chuck F (cbfalconer at maineline dot net)
   <http://cbfalconer.home.att.net>
   Try the download section.



-- 
Posted via a free Usenet account from http://www.teranews.com

On Fri, 16 Nov 2007 19:27:52 -0500, CBFalconer <cbfalconer@yahoo.com>
wrote:

>Vladimir Vassilevsky wrote:
>> larwe wrote:
>> 
>>> In a dynamic processor (ie. one that cannot live if its clock is
>>> stopped), the registers are essentially DRAM cells.
>> 
>> There were two typical architectures for that purpose: two phase and
>> four phase.
>> 
>> The last dynamic CPU probably was the original i8080. Since then all
>> general purpose CPU designs were static.
>
>IIRC the 8080 (and z80) was static. It could be halted without
>harm.

The Z80 and possibly 8085 could have been static, but at least the TI
variant of 8080 (TMS8080) specified 2 us maximum clock cycle time.
Also the 8080 clock driver (8224) had high CPU clock drive capability
(typically required by a dynamic construction). Also MC6800 needed
quite high two phase clock drive capability and the clock frequency
range was specified as 0.1-1 MHz, also suggesting a dynamic
construction.

One of the sales arguments for the CMOS RCA 1802 was that it was fully
static and the clock could be stopped or manually single stepped. This
would suggest that many competitors did not have this capability at
that time-

Paul
 

On Fri, 16 Nov 2007 20:05:18 GMT, in comp.arch.embedded Vladimir
Vassilevsky <antispam_bogus@hotmail.com> wrote:

>
>
>larwe wrote:
>
>> In a dynamic processor (ie. one that cannot live if its clock is
>> stopped), the registers are essentially DRAM cells.
>
>There were two typical architectures for that purpose: two phase and 
>four phase.
>
>The last dynamic CPU probably was the original i8080. Since then all 
>general purpose CPU designs were static.
>
>> If they don't get
>> refreshed, they decay. How much margin you have there to under-clock
>> the device depends on the individual chip production variations,
>> temperature, voltage, etc etc.
>
>The underclocking margin on the modern CPUs is governed by the 
>operational limits of the internal PLL.
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com

Montgomery Scott was suspended in a transporter buffer for over 75
years, due to a power failure,


Martin

Vladimir Vassilevsky wrote:
> larwe wrote:
> 
>> In a dynamic processor (ie. one that cannot live if its clock is
>> stopped), the registers are essentially DRAM cells.
> 
> There were two typical architectures for that purpose: two phase and
> four phase.
> 
> The last dynamic CPU probably was the original i8080. Since then all
> general purpose CPU designs were static.

IIRC the 8080 (and z80) was static. It could be halted without
harm.

-- 
 Chuck F (cbfalconer at maineline dot net)
   <http://cbfalconer.home.att.net>
   Try the download section.



-- 
Posted via a free Usenet account from http://www.teranews.com

"karthikbalaguru" <karthikbalaguru79@gmail.com> wrote in message 
news:6a3a1a12-3b8a-4fd5-95ec-ae0524e800bd@f13g2000hsa.googlegroups.com...
> Hi,
> I came across the below statement -
> "If the oscillator frequency falls below the minimum of a dynamic
> processor, then that processor may suffer corruption of its registers.
> "
>
> How far is that statement true ? (I have not analysed the Registers in
> that condition. Did not
> happen to face that situation ). Regarding the above lines, I think,
> that when the Osciallator
> Frequency falls below the minimum of a dynamic processor, then the
> processor will halt(Stop
> Functioning)/Idle. So, how is it possible for it to suffer from
> Register Corruption ? Need
> clarifications for this.

The registers are made of a type of memory that needs to be refreshed 
periodically.

That is true of a dynamic processor.  A static processor works the way you 
describe.

larwe wrote:

> In a dynamic processor (ie. one that cannot live if its clock is
> stopped), the registers are essentially DRAM cells.

There were two typical architectures for that purpose: two phase and 
four phase.

The last dynamic CPU probably was the original i8080. Since then all 
general purpose CPU designs were static.

> If they don't get
> refreshed, they decay. How much margin you have there to under-clock
> the device depends on the individual chip production variations,
> temperature, voltage, etc etc.

The underclocking margin on the modern CPUs is governed by the 
operational limits of the internal PLL.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

On Nov 16, 8:42 pm, karthikbalaguru <karthikbalagur...@gmail.com>
wrote:
> On Nov 17, 12:22 am, Arlet <usene...@c-scape.nl> wrote:
>
>
>
> > On Nov 16, 8:02 pm, karthikbalaguru <karthikbalagur...@gmail.com>
> > wrote:
>
> > > Hi,
> > > I came across the below statement -
> > > "If the oscillator frequency falls below the minimum of a dynamic
> > > processor, then that processor may suffer corruption of its registers.
> > > "
>
> > > How far is that statement true ? (I have not analysed the Registers in
> > > that condition. Did not
> > > happen to face that situation ). Regarding the above lines, I think,
> > > that when the Osciallator
> > > Frequency falls below the minimum of a dynamic processor, then the
> > > processor will halt(Stop
> > > Functioning)/Idle. So, how is it possible for it to suffer from
> > > Register Corruption ? Need
> > > clarifications for this.
>
> > > Thx in advans,
> > > Karthik Balaguru
>
> > In a dynamic processor, the register contents are stored in very small
> > capacitors, very much like DRAM (http://en.wikipedia.org/wiki/
> > Dynamic_random_access_memory). Unless these registers are refreshed
> > within a certain time, the charges will slowly leak away, and corrupt
> > the data.-
>
> Do you mean to say that the register contents are stored in
> very small capacitors like DRAM in a Processor ?
> (DRAM may need to be refreshed thousands of times per second)
> But, that should making the Processor slow :(:(
> What do you think ?

It doesn't necessarily make the processor slow. It just requires
special consideration in the implementation.

As long as registers are updated during the normal flow of
instructions, they will be automatically refreshed every cycle or
every couple of cycles. For registers that need to keep the same
contents, you just add an extra path from the register back to itself,
so that the old contents will be written again.

>
> There are many varities of DRAM . What kind of DRAM can
> possibly be present inside the processor for storing the register
> contents ? Any ideas ?

The many varieties of DRAM are mostly with regards to the external
interface. The internal design of the single DRAM cell does not vary
much. It's basically a single transistor and some capacitance.

On Nov 17, 12:36 am, larwe <zwsdot...@gmail.com> wrote:
> On Nov 16, 2:34 pm, karthikbalaguru <karthikbalagur...@gmail.com>
> wrote:
>
> > But, how does it play a role with a normal processor ?
>
> What part of the statement is ambiguous?
>
> In a dynamic processor (ie. one that cannot live if its clock is
> stopped), the registers are essentially DRAM cells. If they don't get
> refreshed, they decay. How much margin you have there to under-clock
> the device depends on the individual chip production variations,
> temperature, voltage, etc etc.

Interesting :):)

Karthik Balaguru

On Nov 17, 12:22 am, Arlet <usene...@c-scape.nl> wrote:
> On Nov 16, 8:02 pm, karthikbalaguru <karthikbalagur...@gmail.com>
> wrote:
>
>
>
>
>
> > Hi,
> > I came across the below statement -
> > "If the oscillator frequency falls below the minimum of a dynamic
> > processor, then that processor may suffer corruption of its registers.
> > "
>
> > How far is that statement true ? (I have not analysed the Registers in
> > that condition. Did not
> > happen to face that situation ). Regarding the above lines, I think,
> > that when the Osciallator
> > Frequency falls below the minimum of a dynamic processor, then the
> > processor will halt(Stop
> > Functioning)/Idle. So, how is it possible for it to suffer from
> > Register Corruption ? Need
> > clarifications for this.
>
> > Thx in advans,
> > Karthik Balaguru
>
> In a dynamic processor, the register contents are stored in very small
> capacitors, very much like DRAM (http://en.wikipedia.org/wiki/
> Dynamic_random_access_memory). Unless these registers are refreshed
> within a certain time, the charges will slowly leak away, and corrupt
> the data.-

Do you mean to say that the register contents are stored in
very small capacitors like DRAM in a Processor ?
(DRAM may need to be refreshed thousands of times per second)
But, that should making the Processor slow :(:(
What do you think ?

There are many varities of DRAM . What kind of DRAM can
possibly be present inside the processor for storing the register
contents ? Any ideas ?

Karthik Balaguru