On Feb 22, 5:07=A0pm, "auguste.chin...@googlemail.com"
<auguste.chin...@googlemail.com> wrote:
> Hello,
> Let me right again in this forum on the same topic. But know in
> English. Whatever my English is very poor.
> I am working for about 4 month's ego with an ML405 Xilinx Virtex 4
> board and I =A0 wanted now to implement a Software Defined Radio (SDR).
> I understand everything that relates to SDR (theory, operation,
> Etc..) Very good. Likewise, I also understand VHDL and VERILOG.
> Now I would like to know if someone is thus also employs
> An SDR Board on the above (or others) to implement appropriate
> Experience exchange.
>
> In following a detailed overview of what I Made now:
>
> First, I strive times only to receive an AM signal.
>
> Hardware is on the board as much: =A0DA converter (LM4550)
> National and an external A / D converters (LTC2208) by Linear
> Technology. I have prepared all software developed
> (ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I
> must try my signals: and with a
> Function generator, I would like to generate a sine wave, and then the
> sine wave through the FPGA with the process by the AD and DA
> converters. I Am suppose to have the same signals again after the
> DAC.
>
> Example.
> Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
> I can hear something (signal) at the output (by the DA converter) with
> the
> Headphones. However, I cannot measure it with the oscilloscope.
> I had already tried without much success, and ask what the problem
> Lie? Whether it down sampling, or rather in a
> Clock functions?
>
> Did someone get an idea or a tip for me?
>
> I look forward to all suggestions and thank you in advance...
>

You need to do step-by-step module addition and debugging.
It is better to figure out the method to measure in oscilloscope.
Else, it is going to be tough.

Karthik Balaguru

On 22 Feb, 16:18, "auguste.chin...@googlemail.com"
<auguste.chin...@googlemail.com> wrote:
> On 22 Feb., 15:53, ratemonotonic <niladri1...@gmail.com> wrote:
>
>
>
> > On Feb 22, 12:07 pm, "auguste.chin...@googlemail.com"
>
> > <auguste.chin...@googlemail.com> wrote:
> > > Hello,
> > > Let me right again in this forum on the same topic. But know in
> > > English. Whatever my English is very poor.
> > > I am working for about 4 month's ego with an ML405 Xilinx Virtex 4
> > > board and I   wanted now to implement a Software Defined Radio (SDR).
> > > I understand everything that relates to SDR (theory, operation,
> > > Etc..) Very good. Likewise, I also understand VHDL and VERILOG.
> > > Now I would like to know if someone is thus also employs
> > > An SDR Board on the above (or others) to implement appropriate
> > > Experience exchange.
>
> > > In following a detailed overview of what I Made now:
>
> > > First, I strive times only to receive an AM signal.
>
> > > Hardware is on the board as much:  DA converter (LM4550)
> > > National and an external A / D converters (LTC2208) by Linear
> > > Technology. I have prepared all software developed
> > > (ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I
> > > must try my signals: and with a
> > > Function generator, I would like to generate a sine wave, and then the
> > > sine wave through the FPGA with the process by the AD and DA
> > > converters. I Am suppose to have the same signals again after the
> > > DAC.
>
> > > Example.
> > > Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
> > > I can hear something (signal) at the output (by the DA converter) with
> > > the
> > > Headphones. However, I cannot measure it with the oscilloscope.
> > > I had already tried without much success, and ask what the problem
> > > Lie? Whether it down sampling, or rather in a
> > > Clock functions?
>
> > > Did someone get an idea or a tip for me?
>
> > > I look forward to all suggestions and thank you in advance...
>
> > > Chindji
>
> > Hi ,
>
> > Not enough information. in the chain
>
> > Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
>
> > What are the contents of FPGA? Is it just storing the data from ADC in
> > buffer and transfering to DAC?
>
> The FPAG don't have any contents its just storing the sine wave from
> the ADC and give it out through the DAC.
>
>
>
> > What is the peak to peak of the sine wave ?
>
>  What analog circuitry is
>
> > the sine wave going through?
>
> The sine wave it's just going directly to the ADC
>
> > What is the format of the data comming out of ADC? Any Scaling?
>
>  LVDS (Low Voltage Differential Signaling)
>
> > BR
> > Rate- Zitierten Text ausblenden -
>
> > - Zitierten Text anzeigen -

Right My question about the peak to peak of the signal and the format
of the ADC was to do with saturation issues. Check if the ADC is
saturating or not.

Are you getting anything on the scope?


BR
Rate

On Fri, 22 Feb 2008 04:07:12 -0800, auguste.chindji@googlemail.com wrote:

> Hello,
> Let me right again in this forum on the same topic. But know in English.
> Whatever my English is very poor. I am working for about 4 month's ego
> with an ML405 Xilinx Virtex 4 board and I   wanted now to implement a
> Software Defined Radio (SDR). I understand everything that relates to
> SDR (theory, operation, Etc..) Very good. Likewise, I also understand
> VHDL and VERILOG. Now I would like to know if someone is thus also
> employs An SDR Board on the above (or others) to implement appropriate
> Experience exchange.
> 
> In following a detailed overview of what I Made now:
> 
> First, I strive times only to receive an AM signal.
> 
> Hardware is on the board as much:  DA converter (LM4550) National and an
> external A / D converters (LTC2208) by Linear Technology. I have
> prepared all software developed (ADC.vhd, DAC.vhd, DDC.vhd ,...)I make
> already the simulation. Now, I must try my signals: and with a
> Function generator, I would like to generate a sine wave, and then the
> sine wave through the FPGA with the process by the AD and DA converters.
> I Am suppose to have the same signals again after the DAC.
> 
> 
> Example.
> Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz) I can hear
> something (signal) at the output (by the DA converter) with the
> Headphones. However, I cannot measure it with the oscilloscope. I had
> already tried without much success, and ask what the problem Lie?
> Whether it down sampling, or rather in a Clock functions?
> 
> 
> Did someone get an idea or a tip for me?
> 
> 
> I look forward to all suggestions and thank you in advance...
> 
> 
> Chindji

This would be a good subject to post on comp.dsp -- you'll get about 
equal interest from this newsgroup and sci.electronics.design, but you'll 
get a lot of experienced folks on your side on comp.dsp.

Your post is vague on just what you _do_ see on your oscilloscope, so I 
have a suggestion to start with:  figure out what the signals should be 
going into each stage of your circuit, then build up the application one 
stage at a time, verifying functionality at each step.  You can work from 
either end: you can synthesize a good input signal for the last stage and 
make sure the DAC's do the right thing, then add in the second to last, 
etc.  Conversely, you can bring the output of intermediate stages to the 
DAC and make sure the signals look right.

This is all just basic debugging, but it can be hard to remember to do 
when you're working on a software/firmware app.

-- 
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

On 22 Feb., 15:53, ratemonotonic <niladri1...@gmail.com> wrote:
> On Feb 22, 12:07 pm, "auguste.chin...@googlemail.com"
>
>
>
>
>
> <auguste.chin...@googlemail.com> wrote:
> > Hello,
> > Let me right again in this forum on the same topic. But know in
> > English. Whatever my English is very poor.
> > I am working for about 4 month's ego with an ML405 Xilinx Virtex 4
> > board and I   wanted now to implement a Software Defined Radio (SDR).
> > I understand everything that relates to SDR (theory, operation,
> > Etc..) Very good. Likewise, I also understand VHDL and VERILOG.
> > Now I would like to know if someone is thus also employs
> > An SDR Board on the above (or others) to implement appropriate
> > Experience exchange.
>
> > In following a detailed overview of what I Made now:
>
> > First, I strive times only to receive an AM signal.
>
> > Hardware is on the board as much:  DA converter (LM4550)
> > National and an external A / D converters (LTC2208) by Linear
> > Technology. I have prepared all software developed
> > (ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I
> > must try my signals: and with a
> > Function generator, I would like to generate a sine wave, and then the
> > sine wave through the FPGA with the process by the AD and DA
> > converters. I Am suppose to have the same signals again after the
> > DAC.
>
> > Example.
> > Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
> > I can hear something (signal) at the output (by the DA converter) with
> > the
> > Headphones. However, I cannot measure it with the oscilloscope.
> > I had already tried without much success, and ask what the problem
> > Lie? Whether it down sampling, or rather in a
> > Clock functions?
>
> > Did someone get an idea or a tip for me?
>
> > I look forward to all suggestions and thank you in advance...
>
> > Chindji
>
> Hi ,
>
> Not enough information. in the chain
>
> Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
>
> What are the contents of FPGA? Is it just storing the data from ADC in
> buffer and transfering to DAC?


The FPAG don't have any contents its just storing the sine wave from
the ADC and give it out through the DAC.



>
> What is the peak to peak of the sine wave ?
 What analog circuitry is
> the sine wave going through?

The sine wave it's just going directly to the ADC



> What is the format of the data comming out of ADC? Any Scaling?
 LVDS (Low Voltage Differential Signaling)

> BR
> Rate- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

On Feb 22, 12:07 pm, "auguste.chin...@googlemail.com"
<auguste.chin...@googlemail.com> wrote:
> Hello,
> Let me right again in this forum on the same topic. But know in
> English. Whatever my English is very poor.
> I am working for about 4 month's ego with an ML405 Xilinx Virtex 4
> board and I   wanted now to implement a Software Defined Radio (SDR).
> I understand everything that relates to SDR (theory, operation,
> Etc..) Very good. Likewise, I also understand VHDL and VERILOG.
> Now I would like to know if someone is thus also employs
> An SDR Board on the above (or others) to implement appropriate
> Experience exchange.
>
> In following a detailed overview of what I Made now:
>
> First, I strive times only to receive an AM signal.
>
> Hardware is on the board as much:  DA converter (LM4550)
> National and an external A / D converters (LTC2208) by Linear
> Technology. I have prepared all software developed
> (ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I
> must try my signals: and with a
> Function generator, I would like to generate a sine wave, and then the
> sine wave through the FPGA with the process by the AD and DA
> converters. I Am suppose to have the same signals again after the
> DAC.
>
> Example.
> Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
> I can hear something (signal) at the output (by the DA converter) with
> the
> Headphones. However, I cannot measure it with the oscilloscope.
> I had already tried without much success, and ask what the problem
> Lie? Whether it down sampling, or rather in a
> Clock functions?
>
> Did someone get an idea or a tip for me?
>
> I look forward to all suggestions and thank you in advance...
>
> Chindji

Hi ,

Not enough information. in the chain

Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)

What are the contents of FPGA? Is it just storing the data from ADC in
buffer and transfering to DAC?

What is the peak to peak of the sine wave ? What analog circuitry is
the sine wave going through?

What is the format of the data comming out of ADC? Any Scaling?

BR
Rate

Hello,
Let me right again in this forum on the same topic. But know in
English. Whatever my English is very poor.
I am working for about 4 month's ego with an ML405 Xilinx Virtex 4
board and I   wanted now to implement a Software Defined Radio (SDR).
I understand everything that relates to SDR (theory, operation,
Etc..) Very good. Likewise, I also understand VHDL and VERILOG.
Now I would like to know if someone is thus also employs
An SDR Board on the above (or others) to implement appropriate
Experience exchange.

In following a detailed overview of what I Made now:

First, I strive times only to receive an AM signal.

Hardware is on the board as much:  DA converter (LM4550)
National and an external A / D converters (LTC2208) by Linear
Technology. I have prepared all software developed
(ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I
must try my signals: and with a
Function generator, I would like to generate a sine wave, and then the
sine wave through the FPGA with the process by the AD and DA
converters. I Am suppose to have the same signals again after the
DAC.


Example.
Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
I can hear something (signal) at the output (by the DA converter) with
the
Headphones. However, I cannot measure it with the oscilloscope.
I had already tried without much success, and ask what the problem
Lie? Whether it down sampling, or rather in a
Clock functions?


Did someone get an idea or a tip for me?


I look forward to all suggestions and thank you in advance...


Chindji