On May 30, 3:09 pm, Tom=E1s =D3 h=C9ilidhe <t...@lavabit.com> wrote:
> On May 30, 7:42 pm, Tom=E1s =D3 h=C9ilidhe <t...@lavabit.com> wrote:
>
> > Is there anyway I can get this to work... ? I'm thinking of using one
> > BJT and one FET, and also a pull-up/down resistor. I'll make up a
> > circuit and post a picture.
>
> OK here's what I've got:
>
> http://users.imagine.ie/toe/disp3.JPG
>
> A few points about it:
>
> * Because the source of the NMOS isn't going directly to ground, I
> have to get a FET that has a 4th pin for the bulk.
> * The 10k is a suitable resistor value to put the transistor into
> saturation.
> * The 200k is a pull-down resistor to ensure that the NMOS gate is
> kept low when the uC pin is set to high-impedence. This resistor
> should be as high as possible to ensure that it doesn't provide a
> current path that will turn on the PNP transistor all the time, but at
> the same time it has to be significantly smaller than the output
> resistance of the uC pin to ensure that the entire 5 V is dropped
> within uC, leaving close enough to 0 V across the 200k resistor.
>
> Any thoughts? (..other than the repetitive "get yourself a uC with
> more pins")
I don't see how this circuit will work any better than your other
one. In fact, I think it will work very poorly. I don't think you
are considering the voltages in the circuit. If you have thought
about that, what will the voltage be at the source of the NMOS FET
when it is turned on? What will be the voltage at the emitter of the
BJT when it is turned on? What will be the current in the LED in
either case? What is the voltage on the base of the BJT when the MCU
output is tristate? What will be the current in the two LEDs when the
MCU output is tristate?
Instead of going with exotic parts, why don't you try using a
practical circuit arrangement? Is there a reason that you used an
NMOS FET with a PNP BJT instead of a PMOS FET and an NPN BJT? If you
consider the fact that the BJT has a BE voltage of 0.7 volts when on
and the FET has anywhere from 2 to 5 volts when on, I think you will
find that the BJT is the part you want to use in the emitter follower
configuration, not the FET.
Do you know what an emitter follower is? I believe you are looking at
the components with too simplistic of a model. You need to understand
the difference between current gain and voltage gain and how a FET vs.
a BJT achieve each. The look at the circuit in smaller parts. Just
consider what it will take to turn an LED on at a particular drive
level using both types of FETs and then do the same with BJTs. The
consider what happen with each circuit when the input is undriven.
Only then are you ready to consider how to combine the circuits to do
what you want.
BTW, someone already suggested that you download the Linear Technology
SwitcherCAD (Spice) program to simulate your circuits. This is a very
easy program to use, there is an excellent support group on Yahoo and
you will be able to see *exactly* what is going on without building
anything and burning it up.
The typical design process is to first analyze new circuits using
paper and pencil based on theory. Then simulate the circuit to see if
it behaves as you expect. Only then does an engineer bother to build
a new circuit to test it. Testing is the worst way to verify if
something works because it is *very* hard to test under all
conditions. So you have only proven that the thing works on your
bench, not in real world conditions (which include more than a week
running time). Testing is really done to verify that nothing stupid
was done in the earlier parts. After all, simulation is limited by
the GIGO phenomenon (Garbage In - Garbage Out).
To be honest, your posts here are getting a little old. Not that you
are asking questions, but that you aren't putting much effort into
answering them yourself. Once you have figured out what will work and
what won't, then I would be happy to see you post your circuit and ask
for comments.
Rick
> On May 30, 8:59 pm, Jim Granville <no.s...@designtools.maps.co.nz>
> wrote:
>
>
>>I have already suggested the MOSFET drivers that preserve the
>>3 State Pin sense. Many now do this, to allow lower idle
>>powers in SMPS.
>>
>>Much lower parts count, and no gymnastics.
>
>
>
> Sorry I can't find your post where you mentioned those drivers. Are
> you saying that there's a driver chip out there that will preserve the
> tri-stateness of the uC pin?
Yes,
Devices like this , Drive HL, LH, and LL on Tristate, 2-3A drive spec.
http://www.intersil.com/cda/deviceinfo/0,0,ISL6622A,0.html
It is an emerging design trend in SPMS, to allow the flywheel FET to
not discharge the load in low current situations.
Such devices can also level shift, allowing the LED drive to come from
before the regulator (saves power in the regulator, improves LED load line)
-jg
Reply by ●May 31, 20082008-05-31
On May 30, 8:59=A0pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> I have already suggested the MOSFET drivers that preserve the
> 3 State Pin sense. Many now do this, to allow lower idle
> powers in SMPS.
>
> Much lower parts count, and no gymnastics.
Sorry I can't find your post where you mentioned those drivers. Are
you saying that there's a driver chip out there that will preserve the
tri-stateness of the uC pin?
Reply by Robert Adsett●May 30, 20082008-05-30
In article <b0519651-362b-48ae-ac6d-fa93f7a3b3b8@
59g2000hsb.googlegroups.com>, Tom�s � h�ilidhe says...
> On May 30, 3:06�pm, Andrew Smallshaw <andr...@sdf.lonestar.org> wrote:
>
> > Try redrawing this in a conventional manner, with Vcc at the top.
> > I started looking at this diagram but I lost interest the minute
> > I saw that I was going to have to unravel the circuit before
> > considering it. �There's only so much time people are willing to
> > invest in considering a news post.
>
>
> Are you talking about the way the emitter on the PNP is the bottom pin
> rather than the top pin? If so:
>
> http://users.imagine.ie/toe/disp2.jpg
At this point you can put on a shift register and actually use fewer
pins on the micro.
Robert
** Posted from http://www.teranews.com **
> Any thoughts? (..other than the repetitive "get yourself a uC with
> more pins")
I have already suggested the MOSFET drivers that preserve the
3 State Pin sense. Many now do this, to allow lower idle
powers in SMPS.
Much lower parts count, and no gymnastics.
-jg
Reply by ●May 30, 20082008-05-30
On May 30, 7:42=A0pm, Tom=E1s =D3 h=C9ilidhe <t...@lavabit.com> wrote:
> Is there anyway I can get this to work... ? I'm thinking of using one
> BJT and one FET, and also a pull-up/down resistor. I'll make up a
> circuit and post a picture.
OK here's what I've got:
http://users.imagine.ie/toe/disp3.JPG
A few points about it:
* Because the source of the NMOS isn't going directly to ground, I
have to get a FET that has a 4th pin for the bulk.
* The 10k is a suitable resistor value to put the transistor into
saturation.
* The 200k is a pull-down resistor to ensure that the NMOS gate is
kept low when the uC pin is set to high-impedence. This resistor
should be as high as possible to ensure that it doesn't provide a
current path that will turn on the PNP transistor all the time, but at
the same time it has to be significantly smaller than the output
resistance of the uC pin to ensure that the entire 5 V is dropped
within uC, leaving close enough to 0 V across the 200k resistor.
Any thoughts? (..other than the repetitive "get yourself a uC with
more pins")
Reply by ●May 30, 20082008-05-30
On May 30, 4:53=A0pm, CBFalconer <cbfalco...@yahoo.com> wrote:
> > See this is exactly what I was thinking... but miraculously this
> > worked perfectly in my college project. Even if my board mixed up
> > the collector with the emitter for one of the transistors, it still
> > doesn't explain why both transistors weren't always turned on... ?!
>
> Transistors work with emitter/collector exchanged. =A0Their
> efficiency, Vcc, etc. are sharply curtailed. =A0They are not
> characterized for such operation.
Is there anyway I can get this to work... ? I'm thinking of using one
BJT and one FET, and also a pull-up/down resistor. I'll make up a
circuit and post a picture.
> "MK" <nos...@please.com> wrote:
>
>> In your circuit a big current will flow from VCC through the
>> emitter and out of the base of the first (leftmost) PNP
>> transistor, into the base and out of the emitter of the NPN
>> transistor. The second PNP transistor will turn on, the first
>> two transistors will be destroyed.
>
> See this is exactly what I was thinking... but miraculously this
> worked perfectly in my college project. Even if my board mixed up
> the collector with the emitter for one of the transistors, it still
> doesn't explain why both transistors weren't always turned on... ?!
Transistors work with emitter/collector exchanged. Their
efficiency, Vcc, etc. are sharply curtailed. They are not
characterized for such operation.
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
** Posted from http://www.teranews.com **
Reply by ●May 30, 20082008-05-30
On May 30, 3:53=A0pm, "MK" <nos...@please.com> wrote:
> In your circuit a big current will flow from VCC
> through the emitter and out of the base of the first (leftmost) PNP
> transistor, into the base and out of the emitter of the NPN transistor. Th=
e
> second PNP transistor will turn on, the first two transistors will be
> destroyed.
See this is exactly what I was thinking... but miraculously this
worked perfectly in my college project. Even if my board mixed up the
collector with the emitter for one of the transistors, it still
doesn't explain why both transistors weren't always turned on... ?!
Reply by MK●May 30, 20082008-05-30
"Tom�s � h�ilidhe" <toe@lavabit.com> wrote in message
news:b0519651-362b-48ae-ac6d-fa93f7a3b3b8@59g2000hsb.googlegroups.com...
On May 30, 3:06 pm, Andrew Smallshaw <andr...@sdf.lonestar.org> wrote:
> Try redrawing this in a conventional manner, with Vcc at the top.
> I started looking at this diagram but I lost interest the minute
> I saw that I was going to have to unravel the circuit before
> considering it. There's only so much time people are willing to
> invest in considering a news post.
Are you talking about the way the emitter on the PNP is the bottom pin
rather than the top pin? If so:
http://users.imagine.ie/toe/disp2.jpg
Tomas -
There is a reason for transistor symbols looking a bit like a diode between
the base and emitter. In your circuit a big current will flow from VCC
through the emitter and out of the base of the first (leftmost) PNP
transistor, into the base and out of the emitter of the NPN transistor. The
second PNP transistor will turn on, the first two transistors will be
destroyed.
Why not download SwitcheCAD from www.linear.com and simulate your ciruits.
Michael Kellett
www.mkesc.co.uk