On Sep 9, 2:00=A0pm, "kalyanamsaritha" <kalyanamsari...@gmail.com>
wrote:
> >Every high speed bus needs to be analyzed and designed individually.
> >There really are no shortcuts. =A0I hope this helps.
>
> Excellent explanation!
>
> I may consider just designing in resistors on each high speed bus - at th=
e
> driver and receiver end (on each branch), and populate them accordingly (=
0
> ohm if no significant impedance mismatches)
There are two problems with that idea. The first is that there are
impedance mismatches with the resistors themselves. The impedance of
a signal line is due to its physical size and shape as well as the
dielectric between the trace and ground. Using a resistor that is a
different width will make an impedance mismatch. I can't say if this
mismatch will be a problem or not, but it will be present and be
measurable.
The second problem with this idea is how will you figure out how to
populate these resistors? It is very hard to measure signal
distortion without introducing different (either more or less)
distortion, so it will be hard to adjust them by measurement.
It is not unusual to add arbitrary series resistors near the driver so
that they can be set to a "proper" value at a later date. But adding
resistors at branches is likely to be a very bad idea. If you use
branches, it is best that they are very short relative to the rise
time of the signal, or you have to match impedance by varying the
width of the traces. But you also have to account for the attenuation
at the branch. This can be very tricky.
It is best to create a clear plan on how to deal with the signal
integrity and then to simulate it before building.
Rick
Reply by kalyanamsaritha●September 9, 20082008-09-09
>
>Every high speed bus needs to be analyzed and designed individually.
>There really are no shortcuts. I hope this helps.
>
Excellent explanation!
I may consider just designing in resistors on each high speed bus - at the
driver and receiver end (on each branch), and populate them accordingly (0
ohm if no significant impedance mismatches)
Reply by rickman●September 8, 20082008-09-08
On Sep 8, 6:01=A0pm, "kalyanamsaritha" <kalyanamsari...@gmail.com>
wrote:
> >Absolutely. =A0You will find that your design runs much faster when you
> >can put SDRAM on the board. =A0If you can't get the SDRAM you have
> >designed in, you won't be able to put it on the board. =A0There is also
> >a cost factor.
>
> Thanks for the pointer. Yes, this is SDR SDRAM not DDR.
>
> Now, a few lingering questions on the actual PCB layout for the two
> modules, in particular, the shared signals such as clock, etc.
> 1. How do I lay the traces for such signals? A long trace from the CPU pi=
n
> with a short fork to each of the modules?
> 2. SDR SDRAM being synchronous and all, is it important to length-match?
> Is so, length-matching techniques? I have read about the serpentines, but
> they are known to cause coupling?
> 3. Series termination? The CPU and SDRAM spec do recommend a 33 ohm
> terminator but I never see those on the schematics.
There is no simple approach to dealing with signal integrity (SI)
issues. The various things you mention can help, but none are a magic
bullet and they depend on the details of your design. In its most
simple form, SI problems arise from reflections that occur due to
impedance mismatches. There are three places where you have impedance
mismatches (that I can think of off the top of my head); driver
mismatch to trace, trace to trace (such as a branch or 'T' or stub)
and trace to receiver.
All of these mismatches can cause reflections that can distort the
signal arriving at the receiver. So the best approach is to avoid all
three. But that is seldom possible, much less practical. Another
consideration is the length of the trace compared to the rise time of
the signal. If the round trip time for the length of the trace is
less than 1/4 or so of the rise time of the driver, then the
reflections are unlikely to cause a significant distortion to the
signal. But that requires a total trace length of under 3 inches for
many fast signals.
The effect of driver impedance is to lower the drive voltage of the
incident wave. If the receiver impedance is high, the incident wave
will be reflected with the same polarity bringing the voltage up to a
higher level. If the driver impedance is equal to the line, the
incident wave will be half the driving voltage and the reflected wave
will equal the driving voltage. A single receiver will not see a
distortion since it is the point of reflection. Multiple receivers
will see a stepped voltage at intermediate points. So a series
matching resistor is fully effective only with single receivers.
Reflections at stubs or 'T's are due to the lower impedance at the
junction. This can be made to work if both branches are equal
length. But it requires that the traces be designed to minimize the
impedance mismatch at the 'T'.
Reflections at the receiver can be eliminated by using a parallel
impedance load at the receiver. But this results in a lower voltage
swing and often does not meet threshold specs of the receiver unless
it is designed for a parallel termination such as LVDS or ECL.
Timing on a memory bus can be tricky. It is hard to cause much of a
mismatch on the data/address vs clock, but if you vary the length
enough you can cause problems. Even a couple of inches difference in
length can be tolerated typically. But you need to understand the
detailed timing.
Every high speed bus needs to be analyzed and designed individually.
There really are no shortcuts. I hope this helps.
Rick
Reply by kalyanamsaritha●September 8, 20082008-09-08
>Absolutely. You will find that your design runs much faster when you
>can put SDRAM on the board. If you can't get the SDRAM you have
>designed in, you won't be able to put it on the board. There is also
>a cost factor.
>
Thanks for the pointer. Yes, this is SDR SDRAM not DDR.
Now, a few lingering questions on the actual PCB layout for the two
modules, in particular, the shared signals such as clock, etc.
1. How do I lay the traces for such signals? A long trace from the CPU pin
with a short fork to each of the modules?
2. SDR SDRAM being synchronous and all, is it important to length-match?
Is so, length-matching techniques? I have read about the serpentines, but
they are known to cause coupling?
3. Series termination? The CPU and SDRAM spec do recommend a 33 ohm
terminator but I never see those on the schematics.
Regards.
Reply by rickman●September 7, 20082008-09-07
On Sep 5, 9:04=A0pm, "kalyanamsaritha" <kalyanamsari...@gmail.com>
wrote:
> >> Given SDR SDRAM with 16-bit width, I have seen both 16-bit and 32-bit =
(2
> x
> >> 16-bit) configurations, and am considering which way to go.
>
> >The way which is supported by your SDRAM controller. The controllers and
> >SDRAMs can be quite different and incompatible. Check the documentation
> >for the particular SDRAM and controller in the every detail.
>
> I am looking at existing schematics which are well-vetted. So both
> configurations are quite valid.
>
>
>
> >> What are the pros/cons?
> >> 1. Cost?
> >> 2. Performance?
> >> 3. Ease of board layout?
>
> >There is a lot of other things to consider, such as SDRAM initialization
> >sequence, number of banks, how refresh is implemented, how standby is
> >implemented, timings in clock periods/nanoseconds, what commands are
> >required, what commands are supported, etc. etc.
>
> Assuming this is all a given, is there a tangible performance improvement
> which will offset the cons?
Absolutely. You will find that your design runs much faster when you
can put SDRAM on the board. If you can't get the SDRAM you have
designed in, you won't be able to put it on the board. There is also
a cost factor.
I have not looked at the SDRAM market in some time, but the x16 and
x32 devices ahve much lower production quantities and so are typically
not as low priced as the SDRAMs used in PCs. Of course, if you are
talking about *literally* SDRAM and not DDR or newer, then this is
just not an issue.
I tried to design in x16 SDRAM once and then found I couldn't get
parts. That was some time back when prices were actually going up
instead of down. But the moral is, check out the availability and
longevity of any RAM parts before designing them in. They tend to be
short lived and have a volatile price and delivery.
Rick
Reply by Vladimir Vassilevsky●September 5, 20082008-09-05
kalyanamsaritha wrote:
>>>Given SDR SDRAM with 16-bit width, I have seen both 16-bit and 32-bit (2
>>>16-bit) configurations, and am considering which way to go.
>>
>>The way which is supported by your SDRAM controller.
> I am looking at existing schematics which are well-vetted. So both
> configurations are quite valid.
> Assuming this is all a given, is there a tangible performance improvement
> which will offset the cons?
May be, may be not. It depends. Read the controller manual.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Reply by kalyanamsaritha●September 5, 20082008-09-05
>> Given SDR SDRAM with 16-bit width, I have seen both 16-bit and 32-bit (2
x
>> 16-bit) configurations, and am considering which way to go.
>
>The way which is supported by your SDRAM controller. The controllers and
>SDRAMs can be quite different and incompatible. Check the documentation
>for the particular SDRAM and controller in the every detail.
I am looking at existing schematics which are well-vetted. So both
configurations are quite valid.
>
>> What are the pros/cons?
>> 1. Cost?
>> 2. Performance?
>> 3. Ease of board layout?
>
>There is a lot of other things to consider, such as SDRAM initialization
>sequence, number of banks, how refresh is implemented, how standby is
>implemented, timings in clock periods/nanoseconds, what commands are
>required, what commands are supported, etc. etc.
>
Assuming this is all a given, is there a tangible performance improvement
which will offset the cons?
Reply by Vladimir Vassilevsky●September 5, 20082008-09-05
kalyanamsaritha wrote:
> Given SDR SDRAM with 16-bit width, I have seen both 16-bit and 32-bit (2 x
> 16-bit) configurations, and am considering which way to go.
The way which is supported by your SDRAM controller. The controllers and
SDRAMs can be quite different and incompatible. Check the documentation
for the particular SDRAM and controller in the every detail.
> What are the pros/cons?
> 1. Cost?
> 2. Performance?
> 3. Ease of board layout?
There is a lot of other things to consider, such as SDRAM initialization
sequence, number of banks, how refresh is implemented, how standby is
implemented, timings in clock periods/nanoseconds, what commands are
required, what commands are supported, etc. etc.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Reply by kalyanamsaritha●September 5, 20082008-09-05
Given SDR SDRAM with 16-bit width, I have seen both 16-bit and 32-bit (2 x
16-bit) configurations, and am considering which way to go.
What are the pros/cons?
1. Cost?
2. Performance?
3. Ease of board layout?
[This may have been asked earlier on this forum in some other form ...]
Thanks.