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IntellaSys 40-core Processor Announced
"IntellaSys has unveiled its SEAforth 40C18, a 40-core multicore
processor designed for embedded wireless, portable, and
distributed data processing applications. The SEAforth 40C18
is an array of 40 fully functional CPUs operating asynchronously,
each of the cores a complete computer, with its own ROM, RAM,
and interprocessor communication. Together they can deliver
up to 26 billion operations per second.
"With what IntellaSys claims is the smallest core size design
(0.13 mm2), the SEAforth processor consumes 28 times less power
while running 240 times faster than competing architectures.
By creating a RAM and ROM on each core, individual cores run
at the full native speed of the silicon instead of being
throttled down to a slower external system clock frequency.
The automatic synchronization feature between cores allows
the processors to share the computing load by talking to
each other to pass data, status signals and even code blocks.
When individual CPUs are not active, they automatically shut
down or sleep.
"The beauty of this single-chip 40 CPU processing solution
is that it is completely programmable -- meaning if a spec
changes, it is a code issue, not a silicon turn," said Chuck
Moore, CTO of IntellaSys and inventor of the Forth programming
language. 'With 40 cores operating independently on the chip,
designers can dedicate groups of them to handle specific tasks.
For example, some could be assigned compute-intensive Fast
Fourier Transforms (FFT) while others handle wireless connectivity,
standard I/O interfaces or drive external memory.'
The processor will be offered with VentureForth, a Forth-based
IDE that includes fully interactive programming, testing, and
debugging facilities. VentureForth includes compilers for
both Windows and Linux and a simulator for debugging, and
contains low-level primitives as well as the high-level
tools necessary to map programs across the array of cores
in a SEAforth processor. The SEAforth 40C18 is capable of
executing 80 percent of its VentureForth instructions in
1.38 nanoseconds while drawing 7mW of power or less per CPU.
[...]
"SEAforth Multicore Processors
Formally launched earlier this year, the SEAforth family
of multicore solutions employs an innovative dual-stack
architecture that is both asynchronous and scalable.
The on-chip benefits of initial SEAforth chips coming
to market include:
* RAM and ROM on each core (64 words each) to break the memory bottleneck
* Flash memory interface to ripple-load application code into cores at boot
* Static/dynamic RAM interface to facilitate common data memory access
* Real-time clock support
* 18-bit A/D and 9-bit D/A converters to eliminate need for external data conversion
* Serial (SPI) ports, which can double as I2C and I2S ports
* Extensive parallel I/O lines for versatile �bit banging�
* Scalable connectivity among multiple SEAforth-24 chips via high-speed I/O ports
Forthlet Code Library
Extending the power of the company�s VentureForth software
(RISC derivative of Forth) is the Forthlet Code Library.
Unlike conventional code libraries that require linking
the entire library into the applications program if just
one routine is used, the Forthlet Library links only the
routines used. In this system, there is no penalty for
building a large, comprehensive library. Routines in the
Forthlet Code Library take the form of Forthlet code
objects that can be moved around the chip from core to
core to do special processing. Forthlets are the basic
building blocks of code on the SEA Platform. They are
used in the ROM BIOS in each core, and in the library
of pre-coded functions. Even the user written program
takes the form of a large Forthlet code object that
calls the others.
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Also see:
IntellaSys Offers Free Download of T18 Compiler/Simulator for
SEAforth Multicore Processors Targeting Embedded Applications:
http://www.design-reuse.com/news/?id=14408&print=yes
IntellaSys 40-core Processor Announced:
http://ddj.com/hpc-high-performance-computing/210603583
SEAforth 40C18:
http://www.intellasys.net/index.php?option=com_content&task=view&id=24&Itemid=43
Cores That Share Chores: Single-chip microcontroller houses a number of Forth
processor cores that must cooperate when performing computational tasks:
http://electronicdesign.com/Articles/Print.cfm?AD=1&ArticleID=12692
Multicore processors, FORTH programming, and
the relationship between software and silicon:
http://ddj.com/hpc-high-performance-computing/210603608
A 21st Century Sea Change Taking place in Embedded Microprocessors
http://www.intellasys.net/templates/trial/content/WPEmbMicro.pdf
Modern Forth systems are not like their ancestors:
http://www.ddj.com/embedded/210600604
SEAforth 24:
http://www.intellasys.net/index.php?option=com_content&task=view&id=35&Itemid=63
VentureForth:
http://www.intellasys.net/index.php?option=com_content&task=view&id=57&Itemid=68
SEAforth In Industrial Control and Sensing Applications
http://www.intellasys.net/templates/trial/content/WPControlAndSensing.pdf
Defining Processing Solutions for Mesh Computing Environments
http://www.intellasys.net/templates/trial/content/WPMeshComp.pdf
Interactive Programming and Debugging of Embedded CPU Cores
http://www.intellasys.net/templates/trial/content/WPDebug.pdf
RF Processing Using SEAforth
http://www.intellasys.net/templates/trial/content/WP_RFProcess.pdf
"Natural Language" Programming of Multicore Computers for Control Engineers
http://www.intellasys.net/templates/trial/content/WPBlockDiagramProg.pdf
SEAforth matrix multiplication example:
http://primarycolorforth.blogspot.com/2008/01/seaforth-matrix-multiplication-example.html
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Guy Macon <http://www.GuyMacon.com/> Guy Macon <http://www.GuyMacon.com/>
Guy Macon <http://www.GuyMacon.com/> Guy Macon <http://www.GuyMacon.com/>
Guy Macon <http://www.GuyMacon.com/> Guy Macon <http://www.GuyMacon.com/>
Guy Macon <http://www.GuyMacon.com/> Guy Macon <http://www.GuyMacon.com/>