Handheld Digital Oscilloscope with FFT and Protocol Decoding
Portable handheld digital oscilloscope prototype with FFT analysis and serial protocol decoding.
Advanced Project
— This is advanced because it combines high-speed ADC capture, low-jitter clocking, analog front-end design, real-time DSP/FFT processing, and a portable battery-powered UI in one system.
Assumptions:
- The scope is intended for low-to-moderate bandwidth prototyping, not a lab-grade 100+ MHz instrument.
- Protocol decoding means common digital buses such as UART, I2C, and SPI, not high-speed SERDES.
- The user wants a self-contained portable unit with battery power and a display, rather than a PC-only USB scope.
- A custom analog front end and probe attenuation network will be needed beyond the parts listed here.
Bill of Materials
Compatibility Notes
- ATSAMD51J19A is a 3.3 V MCU, so the ADC, clock generator, display, and storage should also be run at 3.3 V logic levels or level-shifted as needed.
- AD9641BCPZ-80 uses a parallel high-speed digital interface, so PCB layout and pin count are major concerns; the MCU must have enough GPIO and DMA-friendly capture capability.
- SI5338A-B-GM can generate the sampling clock, but the clock distribution and ADC input clock routing need careful low-jitter PCB layout.
- MCP73871-2CCI/ML supports portable battery operation, but the analog front end and display backlight/OLED current must be included in the battery budget.
- If you use a microSD socket instead of SPI flash, the MCU needs a free SPI bus and proper 3.3 V signaling.
You'll Also Need
- Analog front-end parts: input attenuator, AC/DC coupling network, protection diodes, and a fast buffer amplifier are still needed.
- Probe hardware: oscilloscope probe, BNC or SMA input connector, and front-panel attenuation switching are not covered here.
- Mechanical parts: enclosure, knobs, buttons, battery holder, display window, and mounting hardware.
- Passives: precision resistors, capacitors, reference decoupling, ferrites, and clock/ADC supply filtering.
- Firmware: FFT engine, trigger logic, protocol decoder, UI, and capture buffering must be implemented.
- If you want higher bandwidth than a modest prototype scope, the ADC and analog front end will need a more aggressive architecture than this starter BOM.
Estimated BOM Cost: $35-70 (based on live distributor pricing)
Design Considerations
Sampling Architecture
The ADC choice sets the whole instrument class. With AD9641BCPZ-80 at 80 MSPS, you can get useful FFTs and moderate waveform fidelity, but the analog front end and clock quality will dominate real performance. If you try to push bandwidth too far without a proper front end, aliasing and front-end distortion will make the display look better than the measurement really is.
Clock Jitter
For oscilloscope work, sampling clock jitter directly degrades SNR, especially on higher-frequency sine waves. SI5338A-B-GM is flexible, but you still need short routing, solid grounding, and local decoupling near the ADC clock pins. If you later find FFT noise floor issues, the clock tree is one of the first places to investigate.
Analog Front End
A handheld scope lives or dies by its input protection and attenuation network. You will likely need selectable attenuation, clamp protection, and a buffer amplifier before the ADC, because the ADC cannot accept arbitrary probe voltages directly. Keep the analog section physically separated from the MCU and display switching noise.
Firmware Throughput
FFT capture, trigger handling, and protocol decoding are all timing-sensitive, so use DMA and a double-buffered acquisition pipeline. The ATSAMD51J19A can handle this class of workload if you keep the UI and decode tasks decoupled from the capture ISR. A state-machine architecture is much safer than trying to do everything in one interrupt path.
Power Budget
A portable scope can easily draw 200 mA to 500 mA once the display, ADC, clocking, and MCU are active. MCP73871-2CCI/ML simplifies battery charging, but you still need to budget for peak current during backlight or display refresh and ensure the battery can supply it without brownout. Measure quiescent current early, because portable instruments often fail on standby drain rather than active draw.
Validation Strategy
Start by validating the ADC path with a known sine source and a square wave generator before attempting protocol decode. Then verify FFT accuracy against a PC-based reference and confirm trigger stability across temperature and supply variation. For protocol decoding, test with known-good UART, I2C, and SPI captures before trusting live embedded signals.
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