EmbeddedRelated.com
The 2026 Embedded Online Conference
5M40ZE64C5N

ALT5M40ZE64C5N

Altera
CPLD - Complex Programmable Logic Devices
Active

Overview

The 5M40ZE64C5N is a member of Altera's MAX V family of non-volatile, low-power Complex Programmable Logic Devices (CPLDs). It features 40 logic elements, 32 macrocells, and an integrated flash memory block, operating on a single 1.8V core supply with instant-on capability in 0.5 ms or less.

Why Choose This Part

This CPLD offers an instant-on architecture that ensures logic is active before other system components, combined with a standby current as low as 25 uA. The integration of an internal oscillator and user flash memory reduces external component count while the 7.5 ns propagation delay provides fast, predictable timing.

Applications

System Power Sequencing
Managing power-up and power-down timing for multi-rail SoC and FPGA systems.
I/O Level Shifting
Bridging signals between 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V logic levels using MultiVolt I/O support.
Glue Logic Integration
Consolidating discrete logic functions, pulse-width modulators, and simple state machines into a single 64-EQFP package.
Interface Bridging
Implementing low-speed communication protocols or emulated LVDS/RSDS outputs for display and sensor interfaces.

Key Specifications

Mounting Type Surface Mount
Number of I/O 54
Package / Case 64-TQFP Exposed Pad
Programmable Type In System Programmable
Number of Macrocells 32
Delay Time tpd(1) Max 7.5 ns
Operating Temperature 0degC ~ 85degC (TJ)
Supplier Device Package 64-EQFP (7x7)
Voltage Supply - Internal 1.71V ~ 1.89V
Number of Logic Elements/Blocks 40

Getting Started

Development is performed using the Intel Quartus Prime Lite Edition software, which supports VHDL/Verilog entry and simulation. Hardware programming typically requires a USB-Blaster II download cable connected to the JTAG pins of the 64-EQFP package.

Also Consider

EPM240T100C5N Intel (Altera) - Higher density MAX II family device for designs requiring 240 logic elements and more I/O pins.
The 2026 Embedded Online Conference