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CY8C4128LQI-BL543

IFXCY8C4128LQI-BL543

Infineon Technologies
RF Microcontrollers - MCU PSoC4
1,300 in stock

Overview

The CY8C4128LQI-BL543 is a PSoC 4 BLE system-on-chip that combines an Arm Cortex-M0 core with integrated Bluetooth Low Energy (BLE) connectivity. It features programmable analog and digital blocks, including Infineon's CapSense technology for advanced touch-sensing interfaces. Operating at up to 24 MHz with 256 KB of Flash and 32 KB of RAM, it is designed for wireless connectivity in power-constrained environments.

Why Choose This Part

This SoC integrates a complete BLE radio stack and a flexible analog front-end, reducing BOM count for wireless designs. It supports a wide operating voltage range from 1.71V to 5.5V and features 5V-tolerant I/O, providing robust compatibility with various power rails and peripheral logic levels.

Applications

Wireless Human Interface Devices
Implementing Bluetooth-connected keyboards, mice, or remote controls with high-fidelity touch pads using CapSense.
Industrial IoT Sensors
Battery-powered monitoring nodes that require periodic BLE data transmission and local signal conditioning via programmable analog blocks.
Medical Wearables
Low-power fitness trackers or health monitors that utilize the 1.3 uA deep-sleep mode for extended battery life.
Smart Home Controllers
Wall-mounted control panels utilizing the integrated LCD drive and touch-sensing capabilities to manage home automation systems.

Getting Started

Designers should use the PSoC Creator IDE or ModusToolbox for firmware development and hardware configuration of the programmable blocks. The CY8CKIT-042-BLE-A Pioneer Kit is the recommended hardware platform for prototyping and debugging BLE applications. For custom board layouts, ensure proper impedance matching for the integrated RF balun and antenna trace.

Also Consider

EFR32BG22 SiLSilicon Labs - Provides lower active current consumption and higher Flash density for extremely energy-sensitive BLE applications.
STM32WB55 STMicroelectronics - Features a dual-core architecture (Cortex-M4 and Cortex-M0+) for better separation of application logic and the wireless stack.
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