ADIDS28C36Q+T
Overview
The DS28C36Q+T is a high-security DeepCover authenticator that provides a core set of cryptographic tools including ECC-256 and SHA-256 compute engines. It integrates 8192 bits of user EEPROM and a FIPS-rated hardware random number generator to facilitate secure boot, root-of-trust, and anti-counterfeiting measures. The device operates over a standard I2C interface and features an open-drain GPIO for authenticated control applications.
Why Choose This Part
This chip combines asymmetric ECDSA and symmetric SHA-256 logic, providing flexibility for different security architectures without requiring a high-power host processor. It includes a NIST SP 800-90B compliant entropy source for robust key generation and a decrement-only counter for usage-based licensing models.
Applications
Key Specifications
Getting Started
Evaluation requires an I2C-capable host controller and the DS28C36EVKIT evaluation system for rapid prototyping. Engineers should utilize the Maxim Integrated (Analog Devices) software libraries for C-based implementations of the ECDSA and SHA-256 command sequences.
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