MCHPENC28J60/SS
Overview
The ENC28J60/SS is a stand-alone 10Base-T Ethernet controller with an integrated MAC and PHY, designed to serve as an Ethernet network interface for any microcontroller with an SPI port. It features an 8-Kbyte dual-port SRAM buffer for packet storage and hardware-assisted IP checksum calculation to reduce host MCU overhead. This controller allows small embedded systems without native Ethernet peripherals to gain network connectivity using only a few pins.
Why Choose This Part
The integrated PHY and MAC minimize external component count, requiring only an isolation transformer and a few passives to complete the Ethernet interface. The 8-KB onboard SRAM is highly configurable, allowing engineers to optimize the transmit and receive buffer sizes for specific packet traffic patterns. Hardware-level filtering and checksum offloading significantly reduce the processing burden on the host microcontroller.
Applications
Key Specifications
Getting Started
Engineers typically begin evaluation using the Microchip Ethernet Cradle or third-party breakout boards widely available for the SSOP package. Development is supported by the Microchip TCP/IP Stack, and numerous open-source libraries exist for AVR, PIC, and STM32 platforms. Ensure the power supply can provide at least 160mA at 3.1V to 3.6V to handle peak transmission currents.
Also Consider
