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IS25WP128F-JBLE

IS25WP128F-JBLE

ISSI, Integrated Silicon Solution Inc
FLASH - NOR Memory IC 128Mbit SPI - Quad I/O, QPI, DTR 133 MHz 8-SOIC
Active154 in stock

Overview

The IS25WP128F-JBLE is a 128Mbit serial NOR Flash memory device designed for high-performance applications requiring low power consumption and fast data throughput. It operates on a 1.8V supply (1.65V to 1.95V) and supports Quad I/O and Double Transfer Rate (DTR) modes to achieve high effective clock speeds up to 133 MHz. This memory is organized as 16M x 8 and is housed in an 8-pin SOIC package suitable for space-constrained designs.

Why Choose This Part

The device features an extremely low standby current of 8uA and an active read current of 10mA, making it ideal for energy-sensitive designs. Its support for QPI and DTR modes allows for high-bandwidth data transfers that rival traditional parallel flash while using significantly fewer pins. Furthermore, the extended temperature range of -40C to +105C ensures reliability in demanding industrial environments.

Applications

Embedded Firmware Storage
Storing boot code and application firmware for microcontrollers and SoCs that lack internal high-density flash.
Execute-in-Place (XiP)
Running code directly from the external flash memory via high-speed SPI/QPI interfaces to save internal SRAM.
Data Logging
Buffering sensor data or system logs in battery-powered IoT devices where 1.8V operation reduces overall power rail complexity.
FPGA Configuration
Serving as the non-volatile configuration memory for FPGAs that require bitstream loading at power-up.

Key Specifications

Technology FLASH - NOR
Memory Size 128Mbit
Memory Type Non-Volatile
Memory Format FLASH
Mounting Type Surface Mount
Package / Case 8-SOIC (0.209", 5.30mm Width)
Clock Frequency 133 MHz
Memory Interface SPI - Quad I/O, QPI, DTR
Voltage - Supply 1.65V ~ 1.95V
Memory Organization 16M x 8
Operating Temperature -40degC ~ 105degC (TA)
Supplier Device Package 8-SOIC
Write Cycle Time - Word, Page 800us

Getting Started

Engineers can interface this part with any SPI-capable microcontroller or FPGA, ensuring the host controller supports 1.8V I/O levels or using level shifters if necessary. Implementation typically involves using standard SPI flash commands (0x03 for read, 0x02 for page program) or specialized Quad SPI drivers available in frameworks like Zephyr or STM32Cube. For hardware evaluation, verify the 208mil width of the 8-SOIC package to ensure compatibility with standard SOIC-8 footprints which are often 150mil.

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