MCHPLAN91C111-NU
Overview
The LAN91C111-NU is a single-chip 10/100 Ethernet controller with an integrated physical layer (PHY) designed for 3.3V systems. It features a parallel interface with an internal 32-bit wide data path to its 8KB packet buffer memory, optimizing data transfer between the host processor and the network. The device supports full duplex switched Ethernet and includes a flat MMU architecture for efficient packet handling.
Why Choose This Part
It simplifies board design by integrating both the MAC and PHY into a single 128-TQFP package while maintaining 5V tolerant I/O for compatibility with mixed-voltage systems. The 8KB internal RAM and symmetric transmit/receive structures minimize CPU overhead by managing packet queues via an efficient Memory Management Unit (MMU).
Applications
Key Specifications
Getting Started
Designers can configure the device via an optional serial EEPROM interface for persistent MAC address and setting storage. Ensure a stable 25 MHz reference clock is provided to drive both the PHY and MAC, and utilize the MII management serial interface for PHY status monitoring and control.
LAN91C111 Family
| Part Number | Difference | Stock |
|---|---|---|
| LAN91C111-NS | S | 691 |
