MCHPLAN91C111I-NS
Overview
The LAN91C111I-NS is a highly integrated single-chip Ethernet controller combining a 10/100 Mbps MAC and PHY with a flexible parallel interface. It features an internal 32-bit wide data path and 8KB of SRAM for packet buffering, designed to offload networking tasks from the host processor. This industrial-grade component supports both 10Base-T and 100Base-TX standards with integrated wave shaping and an adaptive equalizer.
Why Choose This Part
It offers a flat MMU architecture with symmetric transmit and receive structures, simplifying memory management for the host driver. The device is 5V I/O tolerant while operating on a 3.3V supply, making it versatile for interfacing with various logic levels without external level shifters. Its low-power CMOS design includes enhanced power management features, including a shutdown mode consuming only 15uA.
Applications
Key Specifications
Getting Started
Designers should interface the controller via its parallel host interface and use a 25 MHz reference clock for both the MAC and PHY. Evaluation involves configuring the Serial EEPROM interface for MAC address storage and utilizing the RMII management interface for status monitoring. Reference drivers are typically available for various RTOS environments to accelerate software development.
LAN91C111I Family
| Part Number | Difference | Stock |
|---|---|---|
| LAN91C111I-NU | U | 663 |
