MCHPLAN91C96-MU
Overview
The LAN91C96-MU is a highly integrated single-chip Ethernet controller designed for 10 Base-T networks using a parallel host interface. It features a unique 6 KB internal RAM buffer managed by a hardware Memory Management Unit (MMU) to efficiently handle transmit and receive queues without CPU overhead. This 3.3V CMOS device supports full duplex switched Ethernet and includes an integrated PHY, making it a compact solution for adding networking to embedded processors.
Why Choose This Part
The hardware MMU handles dynamic memory allocation between transmit and receive buffers, effectively eliminating overrun and underrun conditions. Its flat memory structure reduces CPU overhead compared to traditional ring-buffer designs, while the 3.3V low-power CMOS architecture minimizes thermal requirements in 100-TQFP packages.
Applications
Key Specifications
Getting Started
Designers should interface the 16-bit or 8-bit parallel bus directly to the host processor's external memory interface. Initial configuration can be handled via an optional serial EEPROM for jumperless setups, and reference drivers are typically required to manage the proprietary MMU registers. Ensure proper layout for the 10 Base-T differential pairs and magnetics according to the 100-pin TQFP pinout.
LAN91C96 Family
| Part Number | Difference | Stock |
|---|---|---|
| LAN91C96-MS | S | 130 |
