EmbeddedRelated.com
The 2026 Embedded Online Conference
    Parts   FPGAs & CPLDs  Lattice Semiconductor    Lattice CPLDs Family    LC4064V-75TN44C    LC4064V-75TN44C
LC4064V-75TN44C

LC4064V-75TN44C

Lattice Semiconductor Corporation
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Active3,121 in stock
Datasheet Digi-Key Mouser Compare Prices

Overview

The LC4064V-75TN44C is a high-density, 64-macrocell Complex Programmable Logic Device (CPLD) from the ispMACH 4000V series. Operating at 3.3V, it delivers ultra-fast performance with a maximum propagation delay of 7.5 ns and clock speeds reaching up to 322 MHz. It is designed for high-speed logic integration in space-constrained applications using a compact 44-TQFP package.

Why Choose This Part

This CPLD offers a low standby current of 11.5 mA and a typical operating current of 12 mA, making it suitable for power-conscious designs. Its In-System Programmable (ISP) nature via JTAG allows for easy field updates and fast prototyping without removing the chip from the board.

Applications

I/O Expansion
Adding 30 programmable I/O pins to microcontrollers or processors for custom peripheral management.
Interface Bridging
Translating between different bus protocols or voltage levels in high-speed digital systems.
Glueless System Logic
Consolidating multiple discrete logic gates into a single device to reduce PCB footprint and complexity.
Timing and Control
Generating precise clock signals and control sequences for power-sensitive consumer electronics.

Key Specifications

Mounting Type Surface Mount
Number of I/O 30
Package / Case 44-TQFP
Programmable Type In System Programmable
Number of Macrocells 64
Delay Time tpd(1) Max 7.5 ns
Operating Temperature 0degC ~ 90degC (TJ)
Supplier Device Package 44-TQFP (10x10)
Voltage Supply - Internal 3V ~ 3.6V
Number of Logic Elements/Blocks 4

Getting Started

Design entry is typically performed using Lattice Diamond or ispLEVER Classic software, which supports VHDL and Verilog synthesis. Hardware programming is achieved through the integrated JTAG interface using a Lattice USB MachXO/ispMACH programming cable.

Also Consider

EPM240T100C5N Intel Altera - Provides higher logic density (192 macrocells) in the MAX II family if project requirements expand.
ATF1504AS-10AU44 MCHPMicrochip - An alternative 64-macrocell CPLD with 5V tolerant inputs and a pin-compatible 44-pin TQFP package option.

Categories

FPGAs & CPLDs > Lattice Semiconductor FPGAs & CPLDs > CPLDs
The 2026 Embedded Online Conference