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LEO3910PDT-D

LEO3910PDT-D

STMicroelectronics
Linear Voltage Regulator IC Positive Adjustable 1 Output 2A PowerSO-20
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Overview

The LEO3910PDT-D is a positive adjustable linear voltage regulator designed for high-reliability power management, capable of delivering up to 2A of output current. It operates with an input voltage range from 3V to 12V and provides an adjustable output voltage starting from 1.23V up to 9V. Housed in a PowerSO-20 package with an exposed pad, it is engineered for efficient thermal dissipation in demanding environments.

Why Choose This Part

This regulator features integrated antisaturation, over-current, and over-temperature protection to ensure survival in harsh operating conditions. With a 50dB PSRR at 33kHz and a low quiescent current of 62uA, it balances power efficiency with effective noise rejection for sensitive analog rails.

Applications

Space Satellite Power Systems
Used as a local point-of-load regulator for digital and analog circuitry in orbital environments requiring radiation tolerance.
Avionics Instrumentation
Provides stable, low-noise power for flight control computers and sensor interface units where high current and reliability are critical.
High-Reliability Industrial Controls
Acts as a robust regulator in systems requiring internal protection against over-current and over-temperature conditions.

Key Specifications

PSRR 50dB (33kHz)
Output Type Adjustable
Mounting Type Surface Mount
Package / Case 20-PowerSOIC (0.433", 11.00mm Width)
Control Features Inhibit
Current - Output 2A
Protection Features Antisaturation, Over Current, Over Temperature
Number of Regulators 1
Output Configuration Positive
Operating Temperature -40degC ~ 125degC
Voltage - Input (Max) 12V
Voltage Dropout (Max) 1.5V @ 2A
Voltage - Output (Max) 9V
Supplier Device Package PowerSO-20
Current - Quiescent (Iq) 6 mA
Voltage - Output (Min/Fixed) 1.23V

Getting Started

When designing with the LEO3910PDT-D, ensure the PowerSO-20 slug is properly soldered to a large PCB copper plane to manage thermal dissipation at high current loads. The output voltage is set via a resistive divider on the ADJ pin, and an inhibit pin is available for remote power sequencing or low-power standby modes.

Categories

FPGAs & CPLDs