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NB3N1200KMNG

ONNB3N1200KMNG

onsemi
IC 133MHz 1 64-VFQFN Exposed Pad
240 in stock
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Overview

The NB3N1200KMNG is a high-performance 1:12 differential clock buffer designed for PCIe Gen 2 and Gen 3 applications. It features a phase-locked loop (PLL) with configurable bandwidth and a bypass mode for fanout operation, delivering twelve 0.7V HCSL-compatible output pairs. This component is specifically optimized for 100 MHz and 133 MHz frequencies to meet Intel QPI and DB1200Z/ZL standards.

Why Choose This Part

This buffer offers exceptional timing precision with a maximum output-to-output skew of 50 ps and low cycle-to-cycle jitter. The inclusion of SMBus programmability allows for individual output enable control and PLL configuration, providing significant design flexibility. Its spread spectrum compatibility ensures it can track input clock spreading to effectively manage electromagnetic interference (EMI).

Applications

PCI Express Clock Distribution
Distributing high-speed reference clocks for PCIe Gen 2 and Gen 3 bus architectures in server and storage environments.
Network Switches and Routers
Providing low-jitter clocking for high-speed communication hardware requiring multiple synchronized HCSL outputs.
Industrial Computing
Used in high-reliability backplanes where precise timing and low output-to-output skew are critical for data integrity.

Key Specifications

PLL Yes with Bypass
Input Clock
Output HCSL
Mounting Type Surface Mount
Package / Case 64-VFQFN Exposed Pad
Frequency - Max 133MHz
Voltage - Supply 3.135V ~ 3.465V
Divider/Multiplier No/No
Number of Circuits 1
Ratio - Input:Output 1:12
Operating Temperature 0degC ~ 70degC
Supplier Device Package 64-QFN (9x9)
Differential - Input:Output Yes/Yes

Getting Started

Designers should interface with the device via the SMBus to configure the nine selectable addresses and manage individual output pins. Ensure the thermal pad of the 64-VFQFN package is properly soldered to a ground plane to manage the 330mA typical operating current. Decoupling capacitors should be placed as close as possible to the 3.3V VDD pins to maintain low phase jitter performance.