Summary

This blog continues the analysis of a second-order digital phase-locked loop by moving into the Z-domain to derive the discrete-time closed-loop transfer function and characterize response. The reader will learn how loop natural frequency and damping map into discrete coefficients, and how sampling, quantization and implementation choices affect stability and performance.

Key Takeaways

• Derive the discrete-time (Z-domain) closed-loop transfer function for a 2nd-order PLL with a proportional+integral (lead-lag) loop filter.
• Compute loop natural frequency, damping factor and pole locations from the Z-domain representation to predict transient and steady-state behavior.
• Design discrete loop-filter coefficients (and map from continuous-time designs using s-to-z transforms) for a target bandwidth and damping.
• Evaluate sampling, aliasing and fixed-point quantization effects on stability and phase noise/performance.
• Implement and test the phase detector and NCO on embedded platforms (MCU/FPGA) with practical recommendations for coefficient scaling and verification.

Who Should Read This

Embedded firmware and RF/control engineers working on digital PLLs or closed-loop timing systems who need to design or implement discrete-time loop filters and validate stability and performance on microcontrollers or FPGAs.

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