Summary

This blog explains how to use a digital phase-locked loop (DPLL) to lock a digital oscillator or numerically controlled oscillator (NCO) to a 1PPS time reference such as a GPS pulse. It walks through the DPLL concept, phase error measurement, loop filtering and tuning, and practical firmware and hardware considerations for embedded implementations.

Key Takeaways

• Implement a DPLL that measures phase error from 1PPS edges and drives a digital oscillator/NCO
• Measure and filter 1PPS jitter and edge timing to produce a stable phase error signal
• Tune loop parameters (proportional/integral gains and time constants) for stable lock and acceptable settling time
• Integrate the DPLL with microcontroller timers, interrupts, or hardware NCOs and handle quantization limits
• Detect loss-of-lock and implement recovery strategies and validation metrics (phase error, frequency drift)

Who Should Read This

Embedded firmware engineers or system designers with some experience in microcontrollers and timekeeping who need to implement precise time synchronization (e.g., syncing an NCO to GPS 1PPS) in firmware or bare-metal systems.

Still RelevantIntermediate

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